Rename funccov tests to covergroup

Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>

test_regress/t/t_funccov_cross_3way.v

@@ -1,83 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain
-// SPDX-FileCopyrightText: 2026 Matthew Ballance
-// SPDX-License-Identifier: CC0-1.0
-
-// Test 3-way cross coverage
-
-module t;
-    /* verilator lint_off UNSIGNED */
-    bit [7:0] addr;
-    bit [7:0] cmd;
-    bit [7:0] data;
-
-    covergroup cg;
-        a: coverpoint addr {
-            bins low = {[0:1]};
-            bins high = {[2:3]};
-        }
-
-        b: coverpoint cmd {
-            bins read = {0};
-            bins write = {1};
-        }
-
-        c: coverpoint data {
-            bins zero = {0};
-            bins one = {1};
-        }
-
-        // 3-way cross creates 222 = 8 bins
-        abc: cross a, b, c;
-    endgroup
-
-    initial begin
-        cg cg_inst;
-        real cov;
-        int expected_bins;
-
-        cg_inst = new();
-
-        // Total bins: 2 (a) + 2 (b) + 2 (c) + 8 (abc) = 14
-        expected_bins = 14;
-
-        // Hit: lowreadzero
-        addr = 0; cmd = 0; data = 0;
-        cg_inst.sample();
-        cov = cg_inst.get_inst_coverage();
-        // Should have: a.low(1), b.read(1), c.zero(1), abc.low_x__read_x__zero(1) = 4/14 = 28.57%
-        $display("After sample 1: %0.2f%%", cov);
-        if (cov < 25.0 || cov > 32.0) begin
-            $error("Expected ~28.57%%, got %0.2f%%", cov);
-        end
-
-        // Hit: highwriteone
-        addr = 2; cmd = 1; data = 1;
-        cg_inst.sample();
-        cov = cg_inst.get_inst_coverage();
-        // Should have 8/14 = 57.14%
-        $display("After sample 2: %0.2f%%", cov);
-        if (cov < 54.0 || cov > 60.0) begin
-            $error("Expected ~57.14%%, got %0.2f%%", cov);
-        end
-
-        // Hit remaining 6 cross bins
-        addr = 0; cmd = 0; data = 1; cg_inst.sample(); // lowreadone
-        addr = 0; cmd = 1; data = 0; cg_inst.sample(); // lowwritezero
-        addr = 0; cmd = 1; data = 1; cg_inst.sample(); // lowwriteone
-        addr = 2; cmd = 0; data = 0; cg_inst.sample(); // highreadzero
-        addr = 2; cmd = 0; data = 1; cg_inst.sample(); // highreadone
-        addr = 2; cmd = 1; data = 0; cg_inst.sample(); // highwritezero
-
-        cov = cg_inst.get_inst_coverage();
-        $display("After all samples: %0.2f%%", cov);
-        if (cov != 100.0) begin
-            $error("Expected 100%%, got %0.2f%%", cov);
-        end
-
-        $display("3-way cross coverage test PASSED");
-        $write("*-* All Finished *-*\n");
-        $finish;
-    end
-endmodule

test_regress/t/t_funccov_get_coverage.v

@@ -1,53 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain
-// SPDX-FileCopyrightText: 2026 Matthew Ballance
-// SPDX-License-Identifier: CC0-1.0
-
-// Test get_coverage() - type-level coverage exists
-// NOTE: Full instance aggregation not yet implemented
-
-module t;
-    /* verilator lint_off UNSIGNED */
-    bit [7:0] addr;
-
-    covergroup cg;
-        coverpoint addr {
-            bins low = {[0:3]};
-            bins high = {[4:7]};
-        }
-    endgroup
-
-    initial begin
-        cg cg_inst;
-        real type_cov, inst_cov;
-
-        cg_inst = new();
-
-        // Sample some bins
-        addr = 2;
-        cg_inst.sample();
-        addr = 6;
-        cg_inst.sample();
-
-        // Get coverage
-        type_cov = cg::get_coverage();
-        inst_cov = cg_inst.get_inst_coverage();
-
-        $display("Type coverage: %0.2f%%", type_cov);
-        $display("Instance coverage: %0.2f%%", inst_cov);
-
-        // Instance coverage should be 100%
-        if (inst_cov != 100.0) begin
-            $error("Instance coverage should be 100%%, got %0.2f%%", inst_cov);
-        end
-
-        // Type coverage method exists and returns a value (even if 0 for MVP)
-        // Full aggregation across instances requires instance tracking infrastructure
-        $display("get_coverage() method exists and is callable");
-
-        $display("Type coverage test PASSED");
-        $write("*-* All Finished *-*\n");
-        $finish;
-    end
-endmodule

test_regress/t/t_funccov_iff.v

@@ -1,66 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain.
-// SPDX-FileCopyrightText: 2026 Matthew Ballance
-// SPDX-License-Identifier: CC0-1.0
-
-// Test iff condition filtering in coverpoints
-
-module t (/*AUTOARG*/);
-    /* verilator lint_off UNSIGNED */
-    logic [3:0] data;
-    logic       enable;
-
-    covergroup cg;
-        coverpoint data iff (enable) {
-            bins low  = {[0:3]};
-            bins high = {[4:15]};
-        }
-    endgroup
-
-    cg cg_inst;
-
-    initial begin
-        cg_inst = new;
-
-        // Initially no coverage
-        check_coverage(0.0, "initial");
-
-        // Sample with enable=0 - should NOT count
-        enable = 0;
-        data = 1;
-        cg_inst.sample();
-        check_coverage(0.0, "after sample with enable=0");
-
-        // Sample with enable=1 - should count
-        enable = 1;
-        data = 1;
-        cg_inst.sample();
-        check_coverage(50.0, "after sample low with enable=1");
-
-        // Sample high with enable=1
-        enable = 1;
-        data = 10;
-        cg_inst.sample();
-        check_coverage(100.0, "after sample high with enable=1");
-
-        // Sample again with enable=0 - should not affect coverage
-        enable = 0;
-        data = 2;
-        cg_inst.sample();
-        check_coverage(100.0, "after sample with enable=0 again");
-
-        $write("*-* All Finished *-*\n");
-        $finish;
-    end
-
-    task check_coverage(real expected, string label);
-        real cov;
-        cov = cg_inst.get_inst_coverage();
-        $display("Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
-        if (cov < expected - 0.5 || cov > expected + 0.5) begin
-            $error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
-            $stop;
-        end
-    endtask
-endmodule

test_regress/t/t_funccov_sample_basic.py

@@ -1,18 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of either the GNU Lesser General Public License Version 3
-# or the Perl Artistic License Version 2.0.
-# SPDX-FileCopyrightText: 2026 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.compile()
-
-test.execute()
-
-test.passes()