Add toggle test
Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
This commit is contained in:
Ryszard Rozak
parent
44a3e87fc1
commit
6b662a9c25
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// // verilator_coverage annotation
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, check_real, check_array_real, check_string
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);
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000019 input clk;
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input real check_real; // Check issue #2741
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input real check_array_real [1:0];
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input string check_string; // Check issue #2766
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typedef struct packed {
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union packed {
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logic ua;
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logic ub;
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} u;
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logic b;
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} str_t;
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%000002 reg toggle; initial toggle='0;
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%000002 str_t stoggle; initial stoggle='0;
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union {
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real val1; // TODO use bit [7:0] here
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real val2; // TODO use bit [3:0] here
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} utoggle;
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const reg aconst = '0;
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%000002 reg [1:0][1:0] ptoggle; initial ptoggle=0;
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integer cyc; initial cyc=1;
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~000011 wire [7:0] cyc_copy = cyc[7:0];
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%000002 wire toggle_up;
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typedef struct {
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int q[$];
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} str_queue_t;
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str_queue_t str_queue;
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alpha a1 (/*AUTOINST*/
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// Outputs
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.toggle_up (toggle_up),
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc_copy (cyc_copy[7:0]));
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alpha a2 (/*AUTOINST*/
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// Outputs
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.toggle_up (toggle_up),
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc_copy (cyc_copy[7:0]));
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beta b1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle_up (toggle_up));
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off o1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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param#(1) p1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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param#() p2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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%000001 reg [1:0] memory[121:110];
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wire [1023:0] largeish = {992'h0, cyc};
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// CHECK_COVER_MISSING(-1)
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always @ (posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
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toggle <= '0;
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stoggle.u <= toggle;
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stoggle.b <= toggle;
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utoggle.val1 <= real'(cyc[7:0]);
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ptoggle[0][0] <= toggle;
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if (cyc == 3) begin
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str_queue.q.push_back(1);
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toggle <= '1;
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end
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if (cyc == 4) begin
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if (str_queue.q.size() != 1) $stop;
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toggle <= '0;
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end
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else if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module alpha (/*AUTOARG*/
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// Outputs
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toggle_up,
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// Inputs
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clk, toggle, cyc_copy
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);
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// t.a1 and t.a2 collapse to a count of 2
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000038 input clk;
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%000004 input toggle;
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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~000022 input [7:0] cyc_copy;
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// CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22)
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// CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10)
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// CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4)
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// CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2)
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// CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0)
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// CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0)
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// CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
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// CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
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%000004 reg toggle_internal;
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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%000004 output reg toggle_up;
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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always @ (posedge clk) begin
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toggle_internal <= toggle;
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toggle_up <= toggle;
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end
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endmodule
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module beta (/*AUTOARG*/
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// Inputs
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clk, toggle_up
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);
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000019 input clk;
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%000002 input toggle_up;
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// CHECK_COVER(-1,"top.t.b1","toggle_up",2)
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/* verilator public_module */
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always @ (posedge clk) begin
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if (0 && toggle_up) begin end
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end
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endmodule
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module off (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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// verilator coverage_off
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input clk;
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// CHECK_COVER_MISSING(-1)
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// verilator coverage_on
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%000002 input toggle;
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// CHECK_COVER(-1,"top.t.o1","toggle",2)
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endmodule
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module param #(parameter P = 2) (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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000019 input clk;
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%000002 input toggle;
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%000001 logic z;
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for (genvar i = 0; i < P; i++) begin
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%000002 logic x;
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always @ (posedge clk) begin
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x <= toggle;
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end
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for (genvar j = 0; j < 3; j++) begin
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%000003 logic [2:0] y;
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always @ (negedge clk) begin
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y <= {toggle, ~toggle, 1'b1};
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end
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end
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end
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if (P > 1) begin : gen_1
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assign z = 1;
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end
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endmodule
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@ -0,0 +1,52 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_cover_toggle.v"
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test.compile(verilator_flags2=['--cc --coverage --stats'])
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test.execute()
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# Read the input .v file and do any CHECK_COVER requests
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test.inline_checks()
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test.file_grep_not(test.obj_dir + "/coverage.dat", "largeish")
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if test.vlt_all:
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test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 27)
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test.run(cmd=[
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os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",
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"--annotate",
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test.obj_dir + "/annotated",
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test.obj_dir + "/coverage.dat",
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"--filter-type toggle",
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],
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verilator_run=True)
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test.files_identical(test.obj_dir + "/annotated/t_cover_toggle.v", test.golden_filename)
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test.run(cmd=[
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os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",
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"--annotate-points",
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"--annotate",
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test.obj_dir + "/annotated-points",
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test.obj_dir + "/coverage.dat",
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"--filter-type toggle",
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],
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verilator_run=True)
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test.files_identical(test.obj_dir + "/annotated-points/t_cover_toggle.v",
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"t/" + test.name + "__points.out")
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test.passes()
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@ -0,0 +1,303 @@
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// // verilator_coverage annotation
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, check_real, check_array_real, check_string
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);
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000019 input clk;
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+000019 point: comment=clk hier=top.t
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input real check_real; // Check issue #2741
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input real check_array_real [1:0];
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input string check_string; // Check issue #2766
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typedef struct packed {
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union packed {
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logic ua;
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logic ub;
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} u;
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logic b;
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} str_t;
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%000002 reg toggle; initial toggle='0;
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-000002 point: comment=toggle hier=top.t
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%000002 str_t stoggle; initial stoggle='0;
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-000002 point: comment=stoggle.b hier=top.t
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-000002 point: comment=stoggle.u.ua hier=top.t
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union {
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real val1; // TODO use bit [7:0] here
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real val2; // TODO use bit [3:0] here
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} utoggle;
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const reg aconst = '0;
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%000002 reg [1:0][1:0] ptoggle; initial ptoggle=0;
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-000002 point: comment=ptoggle[0][0] hier=top.t
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-000000 point: comment=ptoggle[0][1] hier=top.t
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-000000 point: comment=ptoggle[1][0] hier=top.t
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-000000 point: comment=ptoggle[1][1] hier=top.t
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integer cyc; initial cyc=1;
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~000011 wire [7:0] cyc_copy = cyc[7:0];
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+000011 point: comment=cyc_copy[0] hier=top.t
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-000005 point: comment=cyc_copy[1] hier=top.t
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-000002 point: comment=cyc_copy[2] hier=top.t
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-000001 point: comment=cyc_copy[3] hier=top.t
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-000000 point: comment=cyc_copy[4] hier=top.t
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-000000 point: comment=cyc_copy[5] hier=top.t
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-000000 point: comment=cyc_copy[6] hier=top.t
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-000000 point: comment=cyc_copy[7] hier=top.t
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%000002 wire toggle_up;
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-000002 point: comment=toggle_up hier=top.t
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typedef struct {
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int q[$];
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} str_queue_t;
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str_queue_t str_queue;
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alpha a1 (/*AUTOINST*/
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// Outputs
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.toggle_up (toggle_up),
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc_copy (cyc_copy[7:0]));
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alpha a2 (/*AUTOINST*/
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// Outputs
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.toggle_up (toggle_up),
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc_copy (cyc_copy[7:0]));
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beta b1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle_up (toggle_up));
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off o1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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param#(1) p1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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param#() p2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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%000001 reg [1:0] memory[121:110];
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-000001 point: comment=memory[110][0] hier=top.t
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-000000 point: comment=memory[110][1] hier=top.t
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-000000 point: comment=memory[111][0] hier=top.t
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-000000 point: comment=memory[111][1] hier=top.t
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-000000 point: comment=memory[112][0] hier=top.t
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-000000 point: comment=memory[112][1] hier=top.t
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-000000 point: comment=memory[113][0] hier=top.t
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-000000 point: comment=memory[113][1] hier=top.t
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-000000 point: comment=memory[114][0] hier=top.t
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-000000 point: comment=memory[114][1] hier=top.t
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-000000 point: comment=memory[115][0] hier=top.t
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-000000 point: comment=memory[115][1] hier=top.t
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-000000 point: comment=memory[116][0] hier=top.t
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-000000 point: comment=memory[116][1] hier=top.t
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-000000 point: comment=memory[117][0] hier=top.t
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-000000 point: comment=memory[117][1] hier=top.t
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-000000 point: comment=memory[118][0] hier=top.t
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-000000 point: comment=memory[118][1] hier=top.t
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-000000 point: comment=memory[119][0] hier=top.t
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-000000 point: comment=memory[119][1] hier=top.t
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-000000 point: comment=memory[120][0] hier=top.t
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-000000 point: comment=memory[120][1] hier=top.t
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-000000 point: comment=memory[121][0] hier=top.t
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-000000 point: comment=memory[121][1] hier=top.t
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wire [1023:0] largeish = {992'h0, cyc};
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// CHECK_COVER_MISSING(-1)
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always @ (posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
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toggle <= '0;
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stoggle.u <= toggle;
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stoggle.b <= toggle;
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utoggle.val1 <= real'(cyc[7:0]);
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ptoggle[0][0] <= toggle;
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if (cyc == 3) begin
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str_queue.q.push_back(1);
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toggle <= '1;
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end
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if (cyc == 4) begin
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if (str_queue.q.size() != 1) $stop;
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toggle <= '0;
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end
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else if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module alpha (/*AUTOARG*/
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// Outputs
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toggle_up,
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// Inputs
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clk, toggle, cyc_copy
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);
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// t.a1 and t.a2 collapse to a count of 2
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000038 input clk;
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+000038 point: comment=clk hier=top.t.a*
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%000004 input toggle;
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-000004 point: comment=toggle hier=top.t.a*
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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~000022 input [7:0] cyc_copy;
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+000022 point: comment=cyc_copy[0] hier=top.t.a*
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+000010 point: comment=cyc_copy[1] hier=top.t.a*
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-000004 point: comment=cyc_copy[2] hier=top.t.a*
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-000002 point: comment=cyc_copy[3] hier=top.t.a*
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-000000 point: comment=cyc_copy[4] hier=top.t.a*
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-000000 point: comment=cyc_copy[5] hier=top.t.a*
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-000000 point: comment=cyc_copy[6] hier=top.t.a*
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-000000 point: comment=cyc_copy[7] hier=top.t.a*
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// CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22)
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// CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10)
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// CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4)
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// CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2)
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// CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0)
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// CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0)
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// CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
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// CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
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%000004 reg toggle_internal;
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-000004 point: comment=toggle_internal hier=top.t.a*
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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%000004 output reg toggle_up;
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-000004 point: comment=toggle_up hier=top.t.a*
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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always @ (posedge clk) begin
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toggle_internal <= toggle;
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toggle_up <= toggle;
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end
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endmodule
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module beta (/*AUTOARG*/
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// Inputs
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clk, toggle_up
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);
|
||||
|
||||
000019 input clk;
|
||||
+000019 point: comment=clk hier=top.t.b1
|
||||
|
||||
%000002 input toggle_up;
|
||||
-000002 point: comment=toggle_up hier=top.t.b1
|
||||
// CHECK_COVER(-1,"top.t.b1","toggle_up",2)
|
||||
|
||||
/* verilator public_module */
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (0 && toggle_up) begin end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module off (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk, toggle
|
||||
);
|
||||
|
||||
// verilator coverage_off
|
||||
input clk;
|
||||
// CHECK_COVER_MISSING(-1)
|
||||
|
||||
// verilator coverage_on
|
||||
%000002 input toggle;
|
||||
-000002 point: comment=toggle hier=top.t.o1
|
||||
// CHECK_COVER(-1,"top.t.o1","toggle",2)
|
||||
|
||||
endmodule
|
||||
|
||||
module param #(parameter P = 2) (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk, toggle
|
||||
);
|
||||
|
||||
000019 input clk;
|
||||
+000019 point: comment=clk hier=top.t.p2
|
||||
+000019 point: comment=clk hier=top.t.p1
|
||||
%000002 input toggle;
|
||||
-000002 point: comment=toggle hier=top.t.p2
|
||||
-000002 point: comment=toggle hier=top.t.p1
|
||||
|
||||
%000001 logic z;
|
||||
-000001 point: comment=z hier=top.t.p2
|
||||
-000000 point: comment=z hier=top.t.p1
|
||||
|
||||
for (genvar i = 0; i < P; i++) begin
|
||||
%000002 logic x;
|
||||
-000002 point: comment=genblk1[0].x hier=top.t.p2
|
||||
-000002 point: comment=genblk1[1].x hier=top.t.p2
|
||||
-000002 point: comment=genblk1[0].x hier=top.t.p1
|
||||
always @ (posedge clk) begin
|
||||
x <= toggle;
|
||||
end
|
||||
for (genvar j = 0; j < 3; j++) begin
|
||||
%000003 logic [2:0] y;
|
||||
-000001 point: comment=genblk1[0].genblk1[0].y[0] hier=top.t.p2
|
||||
-000003 point: comment=genblk1[0].genblk1[0].y[1] hier=top.t.p2
|
||||
-000002 point: comment=genblk1[0].genblk1[0].y[2] hier=top.t.p2
|
||||
-000001 point: comment=genblk1[0].genblk1[1].y[0] hier=top.t.p2
|
||||
-000003 point: comment=genblk1[0].genblk1[1].y[1] hier=top.t.p2
|
||||
-000002 point: comment=genblk1[0].genblk1[1].y[2] hier=top.t.p2
|
||||
-000001 point: comment=genblk1[0].genblk1[2].y[0] hier=top.t.p2
|
||||
-000003 point: comment=genblk1[0].genblk1[2].y[1] hier=top.t.p2
|
||||
-000002 point: comment=genblk1[0].genblk1[2].y[2] hier=top.t.p2
|
||||
-000001 point: comment=genblk1[1].genblk1[0].y[0] hier=top.t.p2
|
||||
-000003 point: comment=genblk1[1].genblk1[0].y[1] hier=top.t.p2
|
||||
-000002 point: comment=genblk1[1].genblk1[0].y[2] hier=top.t.p2
|
||||
-000001 point: comment=genblk1[1].genblk1[1].y[0] hier=top.t.p2
|
||||
-000003 point: comment=genblk1[1].genblk1[1].y[1] hier=top.t.p2
|
||||
-000002 point: comment=genblk1[1].genblk1[1].y[2] hier=top.t.p2
|
||||
-000001 point: comment=genblk1[1].genblk1[2].y[0] hier=top.t.p2
|
||||
-000003 point: comment=genblk1[1].genblk1[2].y[1] hier=top.t.p2
|
||||
-000002 point: comment=genblk1[1].genblk1[2].y[2] hier=top.t.p2
|
||||
-000001 point: comment=genblk1[0].genblk1[0].y[0] hier=top.t.p1
|
||||
-000003 point: comment=genblk1[0].genblk1[0].y[1] hier=top.t.p1
|
||||
-000002 point: comment=genblk1[0].genblk1[0].y[2] hier=top.t.p1
|
||||
-000001 point: comment=genblk1[0].genblk1[1].y[0] hier=top.t.p1
|
||||
-000003 point: comment=genblk1[0].genblk1[1].y[1] hier=top.t.p1
|
||||
-000002 point: comment=genblk1[0].genblk1[1].y[2] hier=top.t.p1
|
||||
-000001 point: comment=genblk1[0].genblk1[2].y[0] hier=top.t.p1
|
||||
-000003 point: comment=genblk1[0].genblk1[2].y[1] hier=top.t.p1
|
||||
-000002 point: comment=genblk1[0].genblk1[2].y[2] hier=top.t.p1
|
||||
always @ (negedge clk) begin
|
||||
y <= {toggle, ~toggle, 1'b1};
|
||||
end
|
||||
end
|
||||
end
|
||||
if (P > 1) begin : gen_1
|
||||
assign z = 1;
|
||||
end
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue