luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix input and real loosing real data type, bug501.

This commit is contained in:
Wilson Snyder 2012-05-02 20:53:38 -04:00
parent 6b97673d0a
commit 6aab0f627c
4 changed files with 25 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Changes
View File

@ -23,6 +23,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix ITOD internal error on real conversions, bug491. [Alex Solomatnikov]
**** Fix input and real loosing real data type, bug501. [Alex Solomatnikov]
**** Fix imports causing symbol table error, bug490. [Alex Solomatnikov]
* Verilator 3.833 2012/04/15

2
src/V3AstNodes.h
View File

@ -809,7 +809,7 @@ public:
void addAttrsp(AstNode* nodep) { addNOp4p(nodep); }
AstNode* attrsp() const { return op4p()->castNode(); } // op4 = Attributes during early parse
bool hasSimpleInit() const { return (op3p() && !op3p()->castInitArray()); }
void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); dtypep(nodep); }
void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
void attrClockEn(bool flag) { m_attrClockEn = flag; }
void attrFileDescr(bool flag) { m_fileDescr = flag; }

9
src/V3Link.cpp
View File

@ -313,6 +313,15 @@ private:
|| (findvarp->isSignal() && nodep->isIO())) {
findvarp->combineType(nodep);
nodep->fileline()->modifyStateInherit(nodep->fileline());
AstBasicDType* bdtypep = findvarp->childDTypep()->castBasicDType();
if (bdtypep && bdtypep->implicit()) {
// Then have "input foo" and "real foo" so the dtype comes from the other side.
AstNodeDType* newdtypep = nodep->subDTypep();
if (!newdtypep || !nodep->childDTypep()) findvarp->v3fatalSrc("No child type?");
bdtypep->unlinkFrBack()->deleteTree();
newdtypep->unlinkFrBack();
findvarp->childDTypep(newdtypep);
}
nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
} else {
nodep->v3error("Duplicate declaration of signal: "<<nodep->prettyName());

13
test_regress/t/t_func_real_abs.v
View File

@ -23,12 +23,25 @@ module t (/*AUTOARG*/);
end
endfunction
function integer ceil;
input num;
real num;
if (num > $rtoi(num))
ceil = $rtoi(num) + 1;
else
// verilator lint_off REALCVT
ceil = num;
// verilator lint_on REALCVT
endfunction
initial begin
if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop;
if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop;
if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop;
if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop;
if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop;
if (ceil(-2.1) != -2) $stop;
if (ceil(2.1) != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end