luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

Correctly schedule combinational logic driven from DPI exports.

Browse Source 
Fixes #3429.
This commit is contained in:
Geza Lore
2022-07-14 15:35:49 +01:00
parent ff1b9930fc
commit 6a7bda6910
15 changed files with 330 additions and 117 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3Dead.cpp
+5
View File
@@ -433,6 +433,11 @@ public:
// Operate on whole netlist
iterate(nodep);
if (AstVarScope* const vscp = nodep->dpiExportTriggerp()) {
vscp->user1Inc();
vscp->varp()->user1Inc();
}
deadCheckVar();
// We only eliminate scopes when in a flattened structure
// Otherwise we have no easy way to know if a scope is used