luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-09-04 00:30:34 +02:00
Code Issues Packages Projects Releases Wiki Activity

Internals: Renames for interfaces. No functional change.

Browse Source
This commit is contained in:
Wilson Snyder
2013-05-18 19:45:52 -04:00
parent 2c9dcc3913
commit 6a69813326
6 changed files with 25 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3Delayed.cpp
+3 -3
View File
@@ -124,10 +124,10 @@ private:
AstVar* varp;
AstNodeModule* addmodp = oldvarscp->scopep()->modp();
// We need a new AstVar, but only one for all scopes, to match the new AstVarScope
VarMap::iterator iter = m_modVarMap.find(make_pair(addmodp,name));
if (iter != m_modVarMap.end()) {
VarMap::iterator it = m_modVarMap.find(make_pair(addmodp,name));
if (it != m_modVarMap.end()) {
// Created module's AstVar earlier under some other scope
varp = iter->second;
varp = it->second;
} else {
if (width==0) {
varp = new AstVar (oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, oldvarscp->varp());