Add SELRANGE as warning instead of error, bug477.

Changes

@@ -10,6 +10,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Fix processing unused parametrized modules, bug469, bug470.  [Alex Solomatnikov]
 
+****  Add SELRANGE as warning instead of error, bug477. [Alex Solomatnikov]
+
 ****  Fix signed array warning, bug456. [Alex Solomatnikov]
 
 ****  Fix genvar and begin under generate, bug461.  [Alex Solomatnikov]

bin/verilator

@@ -2771,6 +2771,23 @@ is not possible, add a undef to indicate the code is overriding the value:
     `undef MACRO
     `define MACRO otherdef
 
+=item SELRANGE
+
+Warns that a selection index will go out of bounds:
+
+    wire vec[6:0];
+    initial out = vec[7];  // There is no 7
+
+Verilator will assume zero for this value, instead of X.  Note that in some
+cases this warning may be false, when a condition upstream or downstream of
+the access means the access out of bounds will never execute or be used.
+
+    wire vec[6:0];
+    initial begin
+        seven = 7;
+        ...
+        if (seven != 7) out = vec[seven];  // Never will use vec[7]
+
 =item STMTDLY
 
 Warns that you have a statement with a delayed time in front of it, for

src/V3Const.cpp

@@ -385,7 +385,7 @@ private:
 		else if ((nodep->msbConst() > bdtypep->msbMaxSelect())
 			 || (nodep->lsbConst() > bdtypep->msbMaxSelect())) {
 		    // See also warning in V3Width
-		    nodep->v3error("Selection index out of range: "
+		    nodep->v3warn(SELRANGE, "Selection index out of range: "
 				   <<nodep->msbConst()<<":"<<nodep->lsbConst()
 				   <<" outside "<<bdtypep->msbMaxSelect()<<":0"
 				   <<(bdtypep->lsb()>=0 ? ""

src/V3Error.h

@@ -81,6 +81,7 @@ public:
 	MULTIDRIVEN,	// Driven from multiple blocks
 	REALCVT,	// Real conversion
 	REDEFMACRO,	// Redefining existing define macro
+	SELRANGE,	// Selection index out of range
 	STMTDLY,	// Delayed statement
 	SYMRSVDWORD,	// Symbol is Reserved Word
 	SYNCASYNCNET,	// Mixed sync + async reset
@@ -120,7 +121,7 @@ public:
 	    "LITENDIAN", "MODDUP",
 	    "MULTIDRIVEN",
 	    "REALCVT", "REDEFMACRO",
-	    "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
+	    "SELRANGE", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
 	    "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNSIGNED", "UNUSED",
 	    "VARHIDDEN", "WIDTH", "WIDTHCONCAT",
 	    " MAX"

test_regress/t/t_param_sel_range.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    v_flags2 => ["--lint-only -Wno-SELRANGE"],
+    fails=>0,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_sel_range.v

@@ -0,0 +1,50 @@
+// DESCRIPTION: Verilator: Verilog Test module
+
+// bug477
+
+module t (
+          input  rst_n,
+          input  clk,
+          output out
+          );
+
+   submod #(.STAGES(5)) u2(.*);
+
+endmodule
+
+module submod (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   rst_n, clk
+   );
+
+   parameter STAGES = 4;
+
+   input   rst_n;
+   input   clk;
+   output  out;
+
+   reg [STAGES-1:0] r_rst;
+
+   generate
+      // for i=0..5  (5+1-1)
+      for (genvar i=0; i<STAGES+1-1; i=i+1) begin
+         always @(posedge clk or negedge rst_n) begin
+            if (~rst_n)
+              r_rst[i] <= 1'b0;
+            else begin
+               if (i==0)
+                 r_rst[i] <= 1'b1;
+               else
+                 r_rst[i] <= r_rst[i-1];  // i=0, so -1 wraps to 7
+            end
+         end
+      end
+   endgenerate
+
+   wire out = r_rst[STAGES-1];
+
+endmodule
+
+

test_regress/t/t_param_sel_range_bad.pl

@@ -0,0 +1,29 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+# Really we shouldn't need to warn in this case.
+# When supported, make a new test case that checks the warning
+#$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug477");
+
+top_filename("t/t_param_sel_range.v");
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Warning-SELRANGE: t/t_param_sel_range.v:\d+: Selection index out of range: 7:7 outside 4:0
+%Warning-SELRANGE: Use .* to disable this message.
+%Error: Exiting due to.*',
+    );
+
+ok(1);
+1;