Fix creating implicit variables for expressions, bug196.

Changes

@@ -30,6 +30,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Add Makefile VM_GLOBAL_FAST, listing objects needed to link executables.
 
+**** Fix creating implicit variables for expressions, bug196. [Byron Bradley]
+
 **** Fix MinGW compilation, bug184. [by Shankar Giri]
 
 **** Fix `define argument mis-replacing system task of same name, bug191.

src/V3Link.cpp

@@ -502,9 +502,13 @@ private:
 	    //if (!nodep->modVarp()->rangep()) ...
 	    createImplicitVar(varrefp, false);
 	}
-	else if (AstConcat* concp = nodep->castConcat()) {
-	    pinImplicitExprRecurse(concp->lhsp());
-	    pinImplicitExprRecurse(concp->rhsp());
+	// These are perhaps a little too generous, as a SELect of siga[sigb]
+	// perhaps shouldn't create an implicit variable.  But, we've warned...
+	else {
+	    if (nodep->op1p()) pinImplicitExprRecurse(nodep->op1p());
+	    if (nodep->op2p()) pinImplicitExprRecurse(nodep->op2p());
+	    if (nodep->op3p()) pinImplicitExprRecurse(nodep->op3p());
+	    if (nodep->op4p()) pinImplicitExprRecurse(nodep->op4p());
 	}
     }
 

test_regress/t/t_lint_implicit_port.pl

@@ -0,0 +1,16 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags => ["-Wno-IMPLICIT"],
+	 );
+
+ok(1);
+1;
+

test_regress/t/t_lint_implicit_port.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   logic oe;
+
+   read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) );
+   set  s (.clk(clk), .enable(implicit_write));
+   set  u (.clk(clk), .enable(~implicit_also));
+
+endmodule
+
+module set (
+   input  clk,
+   output enable
+   );
+
+endmodule
+
+module read (
+   input clk,
+   input data
+   );
+
+endmodule