Tests: Fix coverage holes from t_dist_docs_options

docs/gen/ex_DIDNOTCONVERGE_msg.rst

@@ -2,4 +2,4 @@
 .. code-block::
 
    -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] a)
-   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.
+   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries

docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst

@@ -1,4 +1,4 @@
 .. comment: generated by t_lint_didnotconverge_nodbg_bad
 .. code-block::
 
-   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.
+   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries

src/V3Sched.cpp

@@ -167,7 +167,8 @@ AstNodeStmt* checkIterationLimit(AstNetlist* netlistp, const string& name, AstVa
     stmtp->add(callVoidFunc(trigDumpp));
     stmtp->add("#endif\n");
     stmtp->add("VL_FATAL_MT(\"" + V3OutFormatter::quoteNameControls(file) + "\", " + line
-               + ", \"\", \"" + name + " region did not converge.\");");
+               + ", \"\", \"" + name + " region did not converge after " + std::to_string(limit)
+               + " tries\");");
     return ifp;
 }
 

test_regress/t/t_case_huge_noopt.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+test.top_filename = 't/t_case_huge.v'
+
+test.compile(verilator_flags2=["--stats -fno-combine"])
+
+test.file_grep_not(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)')
+
+test.execute()
+
+test.passes()

test_regress/t/t_cover_toggle.out

@@ -27,6 +27,8 @@
         
 %000001    reg   toggle; initial toggle='0;
         
+           logic _under_toggle = toggle;  // For --coverage-underscore
+        
 %000001    str_t stoggle; initial stoggle='0;
         
 ~000010    str_logic strl; initial strl='0;

test_regress/t/t_cover_toggle.py

@@ -33,6 +33,8 @@ test.run(cmd=[
 
 test.files_identical(test.obj_dir + "/annotated/" + test.name + ".v", test.golden_filename)
 
+test.file_grep_not(test.obj_dir + "/coverage.dat", "_under_toggle")
+
 test.run(cmd=[
     os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",
     "--annotate-points",
@@ -45,4 +47,17 @@ test.run(cmd=[
 test.files_identical(test.obj_dir + "/annotated-points/" + test.name + ".v",
                      "t/" + test.name + "__points.out")
 
+test.run(cmd=[
+    os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",
+    "--annotate-all",
+    "--annotate-min 1",
+    "--annotate",
+    test.obj_dir + "/annotated-all",
+    test.obj_dir + "/coverage.dat",
+],
+         verilator_run=True)
+
+test.files_identical(test.obj_dir + "/annotated-all/" + test.name + ".v",
+                     "t/" + test.name + "__all.out")
+
 test.passes()

test_regress/t/t_cover_toggle.v

@@ -26,6 +26,8 @@ module t (/*AUTOARG*/
 
    reg   toggle; initial toggle='0;
 
+   logic _under_toggle = toggle;  // For --coverage-underscore
+
    str_t stoggle; initial stoggle='0;
 
    str_logic strl; initial strl='0;

test_regress/t/t_cover_toggle__all.out

@@ -0,0 +1,260 @@
+//      // verilator_coverage annotation
+        // DESCRIPTION: Verilator: Verilog Test module
+        //
+        // This file ONLY is placed under the Creative Commons Public Domain, for
+        // any use, without warranty, 2008 by Wilson Snyder.
+        // SPDX-License-Identifier: CC0-1.0
+        
+        typedef struct packed {logic a;} str_logic;
+        
+        module t (/*AUTOARG*/
+           // Inputs
+           clk, check_real, check_array_real, check_string
+           );
+        
+ 000010    input clk;
+           input real check_real; // Check issue #2741
+           input real check_array_real [1:0];
+           input string check_string; // Check issue #2766
+        
+           typedef struct packed {
+              union packed {
+                 logic    ua;
+                 logic    ub;
+              } u;
+              logic b;
+           } str_t;
+        
+ 000001    reg   toggle; initial toggle='0;
+        
+           logic _under_toggle = toggle;  // For --coverage-underscore
+        
+ 000001    str_t stoggle; initial stoggle='0;
+        
+ 000010    str_logic strl; initial strl='0;
+        
+           union {
+              real val1;  // TODO use bit [7:0] here
+              real val2;  // TODO use bit [3:0] here
+           } utoggle;
+        
+           const reg aconst = '0;
+        
+~000001    reg [1:0][1:0] ptoggle; initial ptoggle=0;
+        
+           integer cyc; initial cyc=1;
+~000006    wire [7:0] cyc_copy = cyc[7:0];
+ 000001    wire       toggle_up;
+        
+           typedef struct {
+              int q[$];
+           } str_queue_t;
+           str_queue_t str_queue;
+        
+           typedef struct packed {
+              // verilator lint_off ASCRANGE
+              bit [3:5] x;
+              // verilator lint_on ASCRANGE
+              bit [0:0] y;
+           } str_bit_t;
+~000001    str_bit_t str_bit;
+~000001    str_bit_t [5:2] str_bit_arr;
+        
+           assign strl.a = clk;
+        
+           alpha a1 (/*AUTOINST*/
+                     // Outputs
+                     .toggle_up                 (toggle_up),
+                     // Inputs
+                     .clk                       (clk),
+                     .toggle                    (toggle),
+                     .cyc_copy                  (cyc_copy[7:0]));
+           alpha a2 (/*AUTOINST*/
+                     // Outputs
+                     .toggle_up                 (toggle_up),
+                     // Inputs
+                     .clk                       (clk),
+                     .toggle                    (toggle),
+                     .cyc_copy                  (cyc_copy[7:0]));
+        
+           beta  b1 (/*AUTOINST*/
+                     // Inputs
+                     .clk                       (clk),
+                     .toggle_up                 (toggle_up));
+        
+           off   o1 (/*AUTOINST*/
+                     // Inputs
+                     .clk                       (clk),
+                     .toggle                    (toggle));
+        
+           param#(1) p1 (/*AUTOINST*/
+                         // Inputs
+                         .clk                   (clk),
+                         .toggle                (toggle));
+        
+           param#() p2 (/*AUTOINST*/
+                        // Inputs
+                        .clk                    (clk),
+                        .toggle                 (toggle));
+        
+           mod_struct i_mod_struct (/*AUTOINST*/
+                                    // Inputs
+                                    .input_struct   (strl));
+        
+        
+~000001    reg [1:0]  memory[121:110];
+        
+           wire [1023:0] largeish = {992'h0, cyc};
+           // CHECK_COVER_MISSING(-1)
+        
+           always @ (posedge clk) begin
+              if (cyc != 0) begin
+                 cyc <= cyc + 1;
+                 memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
+                 toggle <= '0;
+                 stoggle.u <= toggle;
+                 stoggle.b <= toggle;
+                 utoggle.val1 <= real'(cyc[7:0]);
+                 ptoggle[0][0] <= toggle;
+                 if (cyc == 3) begin
+                    str_queue.q.push_back(1);
+                    toggle <= '1;
+                    str_bit.x <= '1;
+                    str_bit.y <= '1;
+                    str_bit_arr[4].x <= '1;
+                 end
+                 if (cyc == 4) begin
+                    if (str_queue.q.size() != 1) $stop;
+                    toggle <= '0;
+                    str_bit.x[3] <= 0;
+                    str_bit.y[0] <= 0;
+                    str_bit_arr[4].x[3] <= 0;
+                 end
+                 else if (cyc == 10) begin
+                    $write("*-* All Finished *-*\n");
+                    $finish;
+                 end
+              end
+           end
+        
+        endmodule
+        
+        module alpha (/*AUTOARG*/
+           // Outputs
+           toggle_up,
+           // Inputs
+           clk, toggle, cyc_copy
+           );
+        
+           // t.a1 and t.a2 collapse to a count of 2
+        
+ 000020    input clk;
+        
+ 000002    input toggle;
+           // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2)
+           // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2)
+           // (t.a1 and t.a2)
+        
+~000012    input [7:0] cyc_copy;
+           // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12)
+           // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10)
+           // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6)
+           // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4)
+           // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2)
+           // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2)
+           // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2)
+           // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0)
+           // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0)
+           // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0)
+           // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0)
+           // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0)
+           // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0)
+           // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0)
+           // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0)
+           // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0)
+        
+ 000002    reg         toggle_internal;
+           // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2)
+           // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2)
+           // (t.a1 and t.a2)
+        
+ 000002    output reg  toggle_up;
+           // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2)
+           // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2)
+           // (t.a1 and t.a2)
+        
+           always @ (posedge clk) begin
+              toggle_internal <= toggle;
+              toggle_up       <= toggle;
+           end
+        endmodule
+        
+        module beta (/*AUTOARG*/
+           // Inputs
+           clk, toggle_up
+           );
+        
+ 000010    input clk;
+        
+ 000001    input toggle_up;
+           // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1)
+           // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1)
+        
+           /* verilator public_module */
+        
+           always @ (posedge clk) begin
+              if (0 && toggle_up) begin end
+           end
+        endmodule
+        
+        module off (/*AUTOARG*/
+           // Inputs
+           clk, toggle
+           );
+        
+           // verilator coverage_off
+           input clk;
+           // CHECK_COVER_MISSING(-1)
+        
+           // verilator coverage_on
+ 000001    input toggle;
+           // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1)
+           // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1)
+        
+        endmodule
+        
+        module param #(parameter P = 2) (/*AUTOARG*/
+           // Inputs
+           clk, toggle
+           );
+        
+ 000010    input clk;
+ 000001    input toggle;
+        
+~000001    logic z;
+        
+           for (genvar i = 0; i < P; i++) begin
+ 000001       logic x;
+              always @ (posedge clk) begin
+                 x <= toggle;
+              end
+              for (genvar j = 0; j < 3; j++) begin
+~000002          logic [2:0] y;
+                 always @ (negedge clk) begin
+                    y <= {toggle, ~toggle, 1'b1};
+                 end
+              end
+           end
+           if (P > 1) begin : gen_1
+              assign z = 1;
+           end
+        endmodule
+        
+        module mod_struct(/*AUTOARG*/
+           // Inputs
+           input_struct
+           );
+        
+ 000010    input str_logic input_struct;
+        endmodule
+        

test_regress/t/t_cover_toggle__points.out

@@ -31,6 +31,8 @@
 -000001  point: comment=toggle:0->1 hier=top.t
 -000001  point: comment=toggle:1->0 hier=top.t
         
+           logic _under_toggle = toggle;  // For --coverage-underscore
+        
 %000001    str_t stoggle; initial stoggle='0;
 -000001  point: comment=stoggle.b:0->1 hier=top.t
 -000001  point: comment=stoggle.b:1->0 hier=top.t

test_regress/t/t_cover_toggle_underscore.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = 't/t_cover_toggle.v'
+
+test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-underscore'])
+
+test.execute()
+
+test.file_grep(test.obj_dir + "/coverage.dat", "_under_toggle")
+
+test.passes()

test_regress/t/t_debug_emitv.py

@@ -16,7 +16,8 @@ test.lint(
     # Likewise XML
     v_flags=[
         "--lint-only --timing",
-        "--dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv"  # Dev coverage of the V3EmitV code
+        "--dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv",  # Dev coverage of the V3EmitV code
+        "--dump-graph --dumpi-tree-json 9 --no-json-ids"
     ])
 
 output_vs = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*_width.tree.v")

test_regress/t/t_dedupe_clk_gate_off.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+test.top_filename = "t/t_dedupe_clk_gate.v"
+
+test.compile(verilator_flags2=["--stats", "-fno-dedup"])
+
+if test.vlt_all:
+    test.file_grep_not(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)')
+
+test.passes()

test_regress/t/t_dist_docs_options.py

@@ -29,36 +29,14 @@ Test_Waivers = [
     '-gdb',  # Covered: no way to test, part of --gdbbt
     '-rr',  # Not testing; not requiring rr installation
     # Need testing:
-    '-Wno-lint',
-    '-Wno-style',
-    '-Wwarn-lint',
-    '-annotate-all',
-    '-annotate-min',
-    '-converge-limit',
-    '-coverage-underscore',
-    '-default-language',
-    '-dump-graph',
-    '-dumpi-tree-json',
     '-facyc-simp',  # Need test of -fno-...
     '-fassemble',  # Need test of -fno-...
     '-fcase',  # Need test of -fno-...
-    '-fcombine',  # Need test of -fno-...
     '-fconst',  # Need test of -fno-...
-    '-fdedup',  # Need test of -fno-...
     '-fdfg-peephole',  # Need test of -fno-...
     '-fdfg-peephole-',  # Need test of -fno-...
-    '-ffunc-opt-balance-cat',  # Need test of -fno-...
-    '-ffunc-opt-split-cat',  # Need test of -fno-...
-    '-flife',  # Need test of -fno-...
-    '-flife-post',  # Need test of -fno-...
     '-fmerge-cond',  # Need test of -fno-...
-    '-freloop',  # Need test of -fno-...
-    '-fsubst',  # Need test of -fno-...
     '-fsubst-const',  # Need test of -fno-...
-    '-ftable',  # Need test of -fno-...
-    '-json-ids',  # Need test of -no-json-ids
-    '-private',
-    '-trace-depth',
 ]
 
 Sums = {}

test_regress/t/t_flag_language_default.py

@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = 't/t_flag_language.v'
+
+test.compile(verilator_flags2=['--default-language 1364-2001'])
+
+test.execute()
+
+test.passes()

test_regress/t/t_json_only_debugcheck.out

@@ -2548,7 +2548,7 @@
               {"type":"CCALL","name":"","addr":"(BLB)","loc":"a,0:0,0:0","dtypep":"(CB)","funcName":"_dump_triggers__nba","funcp":"(SO)","argsp": []}
             ]},
             {"type":"TEXT","name":"","addr":"(CLB)","loc":"a,0:0,0:0","text":"#endif\n"},
-            {"type":"TEXT","name":"","addr":"(DLB)","loc":"a,0:0,0:0","text":"VL_FATAL_MT(\"t/t_enum_type_methods.v\", 11, \"\", \"NBA region did not converge.\");"}
+            {"type":"TEXT","name":"","addr":"(DLB)","loc":"a,0:0,0:0","text":"VL_FATAL_MT(\"t/t_enum_type_methods.v\", 11, \"\", \"NBA region did not converge after 100 tries\");"}
           ]}
         ],"elsesp": []},
         {"type":"ASSIGN","name":"","addr":"(ELB)","loc":"d,11:8,11:9","dtypep":"(T)",
@@ -2613,7 +2613,7 @@
                 {"type":"CCALL","name":"","addr":"(DMB)","loc":"a,0:0,0:0","dtypep":"(CB)","funcName":"_dump_triggers__act","funcp":"(XN)","argsp": []}
               ]},
               {"type":"TEXT","name":"","addr":"(EMB)","loc":"a,0:0,0:0","text":"#endif\n"},
-              {"type":"TEXT","name":"","addr":"(FMB)","loc":"a,0:0,0:0","text":"VL_FATAL_MT(\"t/t_enum_type_methods.v\", 11, \"\", \"Active region did not converge.\");"}
+              {"type":"TEXT","name":"","addr":"(FMB)","loc":"a,0:0,0:0","text":"VL_FATAL_MT(\"t/t_enum_type_methods.v\", 11, \"\", \"Active region did not converge after 100 tries\");"}
             ]}
           ],"elsesp": []},
           {"type":"ASSIGN","name":"","addr":"(GMB)","loc":"d,11:8,11:9","dtypep":"(T)",

test_regress/t/t_lint_didnotconverge_bad.out

@@ -1,3 +1,3 @@
 -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] a)
-%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.
+%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries
 Aborting...

test_regress/t/t_lint_didnotconverge_nodbg_bad.out

@@ -1,2 +1,2 @@
-%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.
+%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries
 Aborting...

test_regress/t/t_lint_lint_bad.out

@@ -0,0 +1,6 @@
+%Warning-IMPLICIT: t/t_lint_lint_bad.v:9:7: Signal definition not found, creating implicitly: 'implicit_out'
+    9 |   not(implicit_out, i);
+      |       ^~~~~~~~~~~~
+                   ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest
+                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_lint_lint_bad.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(verilator_flags2=["--lint-only -Wwarn-lint"],
+          fails=True,
+          expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_lint_lint_bad.v

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  wire i = 0;
+  not(implicit_out, i);
+endmodule

test_regress/t/t_lint_lint_no.py

@@ -0,0 +1,17 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+test.top_filename = 't/t_lint_lint_bad.v'
+
+test.lint(verilator_flags2=["--lint-only -Wwarn-lint -Wno-lint"])
+
+test.passes()

test_regress/t/t_lint_style_bad.out

@@ -0,0 +1,36 @@
+%Warning-DECLFILENAME: t/t_lint_style_bad.v:7:8: Filename 't_lint_style_bad' does not match MODULE name: 't'
+    7 | module t;
+      |        ^
+                       ... For warning description see https://verilator.org/warn/DECLFILENAME?v=latest
+                       ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message.
+%Warning-VARHIDDEN: t/t_lint_style_bad.v:12:14: Declaration of signal hides declaration in upper scope: 'top'
+   12 |       output top;
+      |              ^~~
+                    t/t_lint_style_bad.v:9:12: ... Location of original declaration
+    9 |    integer top;
+      |            ^~~
+                    ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest
+                    ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message.
+%Warning-VARHIDDEN: t/t_lint_style_bad.v:18:18: Declaration of signal hides declaration in upper scope: 'top'
+   18 |          integer top;
+      |                  ^~~
+                    t/t_lint_style_bad.v:9:12: ... Location of original declaration
+    9 |    integer top;
+      |            ^~~
+%Warning-UNUSEDSIGNAL: t/t_lint_style_bad.v:9:12: Signal is not driven, nor used: 'top'
+                                                : ... note: In instance 't'
+    9 |    integer top;
+      |            ^~~
+                       ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest
+                       ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message.
+%Warning-UNDRIVEN: t/t_lint_style_bad.v:12:14: Signal is not driven: 'top'
+                                             : ... note: In instance 't'
+   12 |       output top;
+      |              ^~~
+                   ... For warning description see https://verilator.org/warn/UNDRIVEN?v=latest
+                   ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message.
+%Warning-UNUSEDSIGNAL: t/t_lint_style_bad.v:18:18: Signal is not driven, nor used: 'top'
+                                                 : ... note: In instance 't'
+   18 |          integer top;
+      |                  ^~~
+%Error: Exiting due to

test_regress/t/t_lint_style_bad.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(verilator_flags2=["--lint-only -Wwarn-style"],
+          fails=True,
+          expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_lint_style_bad.v

@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   integer top;
+
+   task x;
+      output top;
+      begin end
+   endtask
+
+   initial begin
+      begin: lower
+         integer top;
+      end
+   end
+
+endmodule

test_regress/t/t_lint_style_no.py

@@ -0,0 +1,17 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+test.top_filename = 't/t_lint_style_bad.v'
+
+test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-style"])
+
+test.passes()

test_regress/t/t_math_real_private.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = 't/t_math_real_public.v'
+
+# Test that --private overrides --public
+test.compile(verilator_flags2=['--cc --public --private'])
+
+test.execute()
+
+test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "___024root.h", r'REAL_PARAM')
+
+test.passes()

test_regress/t/t_math_real_public.py

@@ -15,4 +15,6 @@ test.compile(verilator_flags2=['--cc --public'])
 
 test.execute()
 
+test.file_grep(test.obj_dir + "/" + test.vm_prefix + "___024root.h", r'REAL_PARAM')
+
 test.passes()

test_regress/t/t_math_real_public.v

@@ -5,14 +5,14 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-   sub #(.REAL(2.0)) sub();
+   sub #(.REAL_PARAM(2.0)) sub();
 endmodule
 
 module sub ();
-   parameter REAL = 0.0;
+   parameter REAL_PARAM = 0.0;  // Magic name grepped for in .py file
 
    initial begin
-      $display("REAL %g", REAL);
+      $display("REAL_PARAM=%g", REAL_PARAM);
       $write("*-* All Finished *-*\n");
       $finish;
    end

test_regress/t/t_opt_life_off.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+test.top_filename = "t/t_opt_life.v"
+
+test.compile(verilator_flags2=['--stats', '-fno-life', '-fno-life-post'])
+
+if test.vlt_all:
+    test.file_grep_not(test.stats, r'Optimizations, Lifetime assign deletions\s+(\d+)')
+    test.file_grep_not(test.stats, r'Optimizations, Lifetime creset deletions\s+(\d+)')
+    test.file_grep_not(test.stats, r'Optimizations, Lifetime constant prop\s+(\d+)')
+    test.file_grep_not(test.stats, r'Optimizations, Lifetime postassign deletions\s+(\d+)')
+
+test.passes()

test_regress/t/t_opt_subst.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+
+test.compile(verilator_flags2=["--stats"])
+
+if test.vlt_all:
+    test.file_grep(test.stats, r'Optimizations, Substituted temps\s+(\d+)', 42)
+
+test.execute()
+
+test.passes()

test_regress/t/t_opt_subst.v

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// Copyright 2025 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module t (
+    input clk
+);
+
+  integer i;
+  reg [94:0] w95;
+
+  integer cyc = 0;
+
+  // Test loop
+  always @(posedge clk) begin
+`ifdef TEST_VERBOSE
+    $write("[%0t] cyc==%0d\n", $time, cyc);
+`endif
+    cyc <= cyc + 1;
+    if (cyc == 0) begin
+      // Setup
+      w95 = {95{1'b1}};
+    end
+    else if (cyc == 1) begin
+      if (w95++ != {95{1'b1}}) $stop;
+      if (w95 != {95{1'b0}}) $stop;
+      if (w95-- != {95{1'b0}}) $stop;
+      if (w95 != {95{1'b1}}) $stop;
+      if (++w95 != {95{1'b0}}) $stop;
+      if (w95 != {95{1'b0}}) $stop;
+      if (--w95 != {95{1'b1}}) $stop;
+      if (w95 != {95{1'b1}}) $stop;
+    end
+    else if (cyc == 99) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+endmodule

test_regress/t/t_opt_subst_off.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+test.top_filename = "t/t_opt_life.v"
+
+test.compile(verilator_flags2=['--stats', '-fno-subst'])
+
+if test.vlt_all:
+    test.file_grep_not(test.stats, r'Optimizations, Substituted temps\s+(\d+)')
+
+test.passes()

test_regress/t/t_opt_table_real_off.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+test.top_filename = 't/t_opt_table_real.v'
+test.golden_filename = 't/t_opt_table_real.out'
+
+test.compile(verilator_flags2=["--stats -fno-table"])
+
+if test.vlt_all:
+    test.file_grep_not(test.stats, r'Optimizations, Tables created\s+(\d+)')
+
+test.execute(expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_reloop_cam_off.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+test.top_filename = "t/t_reloop_cam.v"
+
+test.compile(verilator_flags2=["--stats", "-fno-reloop"])
+
+if test.vlt_all:
+    test.file_grep_not(test.stats, r'Optimizations, Reloop iterations\s+(\d+)')
+    test.file_grep_not(test.stats, r'Optimizations, Reloops\s+(\d+)')
+
+test.passes()

test_regress/t/t_trace_depth.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+test.compile(v_flags2=["--trace-vcd --trace-depth 1"])
+
+test.execute()
+
+test.file_grep(test.trace_filename, r'value_at_top')
+test.file_grep_not(test.trace_filename, r' value_in_sub')
+
+test.passes()

test_regress/t/t_trace_depth.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    input clk
+);
+
+  int cyc;
+  wire integer value_at_top = cyc;  // Magic name checked in .py file
+
+  sub1 sub1a (.*);
+  sub1 sub1b (.*);
+
+  always @(posedge clk) begin
+    cyc <= cyc + 1;
+    if (cyc == 10) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+
+endmodule
+
+module sub1 (
+    input int cyc
+);
+
+  sub2 sub2a (.*);
+  sub2 sub2b (.*);
+  sub2 sub2c (.*);
+endmodule
+
+module sub2 (
+    input int cyc
+);
+
+  wire integer value_in_sub = cyc;  // Magic name checked in .py file
+endmodule

test_regress/t/t_unopt_converge_initial_run_bad.out

@@ -1,3 +1,3 @@
 -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] x)
-%Error: t/t_unopt_converge_initial.v:7: Settle region did not converge.
+%Error: t/t_unopt_converge_initial.v:7: Settle region did not converge after 100 tries
 Aborting...

test_regress/t/t_unopt_converge_ndbg_bad.out

@@ -1,2 +1,2 @@
-%Error: t/t_unopt_converge.v:7: Settle region did not converge.
+%Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries
 Aborting...

test_regress/t/t_unopt_converge_print_bad.out

@@ -1,3 +1,3 @@
 -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] x)
-%Error: t/t_unopt_converge.v:7: Settle region did not converge.
+%Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries
 Aborting...

test_regress/t/t_unopt_converge_run_bad.out

@@ -1,3 +1,3 @@
 -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] x)
-%Error: t/t_unopt_converge.v:7: Settle region did not converge.
+%Error: t/t_unopt_converge.v:7: Settle region did not converge after 5 tries
 Aborting...

test_regress/t/t_unopt_converge_run_bad.py

@@ -12,7 +12,8 @@ import vltest_bootstrap
 test.scenarios('simulator')
 test.top_filename = "t/t_unopt_converge.v"
 
-test.compile(v_flags2=['+define+ALLOW_UNOPT', '--output-split 0', "-fno-dfg"])
+test.compile(
+    v_flags2=['+define+ALLOW_UNOPT', '--output-split 0', '-fno-dfg', '--converge-limit 5'])
 
 if test.vlt_all:
     test.execute(fails=True, expect_filename=test.golden_filename)