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Make class ref typing stricter (#3671)
Prevents the possibility of assigning an integer to a class reference, both at the SystemVerilog and the emitted C++ levels. Signed-off-by: Krzysztof Bieganski <[email protected]>
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+10
-3
@@ -506,7 +506,6 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const {
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out << "'";
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if (bitIs0(0)) {
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out << '0';
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if (isNull()) out << "[null]";
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} else if (bitIs1(0)) {
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out << '1';
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} else if (bitIsZ(0)) {
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@@ -542,7 +541,13 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const {
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// Always deal with 4 bits at once. Note no 4-state, it's above.
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out << displayed("%0h");
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}
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if (isNull() && VL_UNCOVERABLE(!isEqZero())) out << "-%E-null-not-zero";
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if (isNull()) {
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if (VL_UNCOVERABLE(!isEqZero())) {
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out << "-%E-null-not-zero";
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} else {
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out << " [null]";
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}
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}
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return out.str();
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}
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@@ -2169,7 +2174,9 @@ V3Number& V3Number::opAssignNonXZ(const V3Number& lhs, bool ignoreXZ) {
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// to itself; V3Simulate does this when hits "foo=foo;"
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// So no: NUM_ASSERT_OP_ARGS1(lhs);
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if (this != &lhs) {
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if (isString()) {
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if (VL_UNLIKELY(lhs.isNull())) {
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m_data.m_isNull = true;
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} else if (isString()) {
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if (VL_UNLIKELY(!lhs.isString())) {
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// Non-compatible types, erase value.
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m_data.str() = "";
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