Support declarations in loop initializers, bug172.

Changes

@@ -5,20 +5,16 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.7**
 
-***  Support byte, shortint, int, longint and var in variables, parameters and
+**   Support byte, shortint, int, longint, var and void in variables, parameters and
      functions.
 
-***  Support void functions.
+**   Support "program", "package", "import" and $unit.
 
-***  Support "reg [1:0][1:0][1:0]", bug176.  [Byron Bradley]
+**   Support typedef.  [Donal Casey]
 
-***  Support "reg x [3][2]".
+***  Support "reg [1:0][1:0][1:0]" and "reg x [3][2]", bug176.  [Byron Bradley]
 
-***  Support "program".
-
-***  Support "package", "import" and $unit.
-
-***  Support typedef.  [Donal Casey]
+***  Support declarations in loop initializers, bug172.  [by Bryon Bradley]
 
 ***  Add VARHIDDEN warning when signal name hides module name.
 

src/verilog.y

@@ -1706,7 +1706,7 @@ statement_item<nodep>:		// IEEE: statement_item
 	|	yWHILE '(' expr ')' stmtBlock		{ $$ = new AstWhile($1,$3,$5);}
 	//			// for's first ';' is in for_initalization
 	|	yFOR '(' for_initialization expr ';' for_stepE ')' stmtBlock
-							{ $$ = new AstFor($1, $3,$4,$6, $8);}
+							{ $$ = new AstBegin($1,"",$3); $3->addNext(new AstFor($1,NULL,$4,$6,$8));}
 	|	yDO stmtBlock yWHILE '(' expr ')'	{ $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));}
 	//UNSUP	yFOREACH '(' idClassForeach/*array_id[loop_variables]*/ ')' stmt	{ UNSUP }
 	//
@@ -1819,7 +1819,11 @@ caseCondList<nodep>:		// IEEE: part of case_item
 // "datatype id = x {, id = x }"  |  "yaId = x {, id=x}" is legal
 for_initialization<nodep>:	// ==IEEE: for_initialization + for_variable_declaration + extra terminating ";"
 	//			// IEEE: for_variable_declaration
-		varRefBase '=' expr ';'			{ $$ = new AstAssign($2,$1,$3); }
+		data_type idAny/*new*/ '=' expr ';'
+			{ VARDTYPE($1);
+			  $$ = VARDONEA(*$2,NULL,NULL);
+			  $$->addNext(new AstAssign($3,new AstVarRef($3,*$2,true),$4));}
+	|	varRefBase '=' expr ';'			{ $$ = new AstAssign($2,$1,$3); }
 	//UNSUP: List of initializations
 	;
 

test_regress/t/t_for_local.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_for_local.v

@@ -0,0 +1,53 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   reg [7:0] cyc; initial cyc=0;
+
+   reg [31:0] loops;
+   reg [31:0] loops2;
+
+   always @ (posedge clk) begin
+      cyc <= cyc+8'd1;
+      if (cyc == 8'd1) begin
+	 $write("[%0t] t_loop: Running\n",$time);
+	 // Unwind <
+	 loops = 0;
+	 loops2 = 0;
+	 for (int i=0; i<16; i=i+1) begin
+	    loops = loops + i;		// surefire lint_off_line ASWEMB
+	    loops2 = loops2 + i;	// surefire lint_off_line ASWEMB
+	 end
+	 if (loops !== 120) $stop;
+	 if (loops2 !== 120) $stop;
+	 // Check we can declare the same signal twice
+	 loops = 0;
+	 for (int i=0; i<=16; i=i+1) begin
+	    loops = loops + 1;
+	 end
+	 if (loops !== 17) $stop;
+	 // Check type is correct
+	 loops = 0;
+	 for (byte unsigned i=5; i>4; i=i+1) begin
+	    loops = loops + 1;
+	 end
+	 if (loops !== 251) $stop;
+	 // Check large loops
+	 loops = 0;
+	 for (int i=0; i<100000; i=i+1) begin
+	    loops = loops + 1;
+	 end
+	 if (loops !== 100000) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule