Tests: bug1104, unsupported.

src/verilog.y

@@ -868,9 +868,9 @@ port<nodep>:			// ==IEEE: port
 			  VARDTYPE(new AstIfaceRefDType($<fl>2,"",*$2,*$4));
 			  $$->addNextNull(VARDONEP($$,$6,$7)); }
 	|	portDirNetE yINTERFACE                           portSig rangeListE sigAttrListE
-			{ $<fl>2->v3error("Unsupported: virtual interfaces"); $$=NULL; }
+			{ $<fl>2->v3error("Unsupported: virtual or generic interfaces"); $$=NULL; }
 	|	portDirNetE yINTERFACE      '.' idAny/*modport*/ portSig rangeListE sigAttrListE
-			{ $<fl>2->v3error("Unsupported: virtual interfaces"); $$=NULL; }
+			{ $<fl>2->v3error("Unsupported: virtual or generic interfaces"); $$=NULL; }
 	//
 	//			// IEEE: ansi_port_declaration, with [port_direction] removed
 	//			//   IEEE: [ net_port_header | interface_port_header ] port_identifier { unpacked_dimension } [ '=' constant_expression ]

test_regress/t/t_interface_param2.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug1104");
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_param2.v

@@ -0,0 +1,46 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Adrian Wise
+
+//bug1104
+
+module t (input clk);
+   simple_bus sb_intf(clk);
+   simple_bus #(.DWIDTH(16)) wide_intf(clk);
+   mem mem(sb_intf.slave);
+   cpu cpu(sb_intf.master);
+   mem memW(wide_intf.slave);
+   cpu cpuW(wide_intf.master);
+endmodule
+
+interface simple_bus #(AWIDTH = 8, DWIDTH = 8)
+   (input logic clk); // Define the interface
+
+   logic req, gnt;
+   logic [AWIDTH-1:0] addr;
+   logic [DWIDTH-1:0] data;
+
+   modport slave( input req, addr, clk,
+		  output gnt,
+		  input  data);
+
+   modport master(input gnt, clk,
+		  output req, addr,
+		  output data);
+
+endinterface: simple_bus
+
+module mem(interface a);
+   logic avail;
+   always @(posedge a.clk)
+     a.gnt <= a.req & avail;
+   initial begin
+      if ($bits(a.data != 16)) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module cpu(interface b);
+endmodule