Commentary: Changes update

Changes

@@ -22,7 +22,7 @@ Verilator 5.047 devel
 * Add `--func-recursion-depth` option (#7175) (#7179).
 * Add `+verilator+solver+file` for debugging constraint solver (#7242).
 * Add `--coverage-fsm` for experimental FSM state and arc coverage (#7412). [Yogish Sekhar]
-* Add printed summary to verilator_coverage (#7438). [Yogish Sekhar]
+* Add printed summary to verilator_coverage (#7438) (#7462). [Yogish Sekhar]
 * Deprecate `--structs-packed` (#7222).
 * Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.]
 * Remove multi-threaded FST tracing (#7443). [Geza Lore, Testorrent USA, Inc.]
@@ -58,6 +58,7 @@ Verilator 5.047 devel
 * Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
 * Support property-local variables and sequence match items (#7286). [Yilou Wang]
 * Support 'until' and `until_with` property (#7290 partial) (#7399) (#7436). [Ryszard Rozak, Antmicro Ltd.]
+* Support implication operator with constraint_set (#7300) (#7448). [Yilou Wang]
 * Support array map() method (#7307) (#7316) (#7344). [Wei-Lun Chiu]
 * Support MacOS address sanitizer memory limit (#7308). [Marco Bartoli]
 * Support SVA goto repetition `[->N]` in concurrent assertions (#7310). [Yilou Wang]
@@ -91,6 +92,7 @@ Verilator 5.047 devel
 * Optimize temporary insertion in DfgPeephole. [Geza Lore, Testorrent USA, Inc.]
 * Optimize arithmetic right shift (>>>) in DfgBreakCycles (#7447). [Geza Lore, Testorrent USA, Inc.]
 * Optimize temporary insertion in DFG (#7459). [Geza Lore, Testorrent USA, Inc.]
+* Optimize mix of Concat/Extend assignments (#7479). [Geza Lore, Testorrent USA, Inc.]
 * Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
 * Fix tracing virtual interface member written from classes (#5044) (#7465). [Nikolay Puzanov]
 * Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang]
@@ -167,6 +169,10 @@ Verilator 5.047 devel
 * Fix modification of members of object with const handle (#7433). [Kamil Danecki, Antmicro Ltd.]
 * Fix `dist` under implication in constraints (#7440) (#7442). [Alex Solomatnikov] [Yilou Wang]
 * Fix std::randomize `inside` corrupting class-member queue operand (#7449) (#7456). [Yilou Wang]
+* Fix function-in-constraint internal error on bare port return (#7473) (#7480). [Yilou Wang]
+* Fix access to static variable inside function (#7474) (#7475). [Alex Zhou]
+* Fix std::randomize inside {typedef array} internal error (#7481). [Yilou Wang]
+* Fix module parameters not re-evaluated upon instantiation (#7463) (#7477). [em2machine]
 
 
 Verilator 5.046 2026-02-28

test_regress/t/t_constraint_func_call_root_varref.v

@@ -52,9 +52,9 @@ endclass
 
 module t;
   FassignBody o1;
-  Freturn    o2;
-  Fmultiarg  o3;
-  Fnonrand   o4;
+  Freturn o2;
+  Fmultiarg o3;
+  Fnonrand o4;
   int rand_ok;
 
   initial begin

test_regress/t/t_constraint_implication_set.v

@@ -16,14 +16,14 @@ typedef enum bit [1:0] { TXN_READ, TXN_WRITE } txn_e;
 // (constraint_set on the right of the implication operator -> ).  `mode`
 // selects which constraint contributes; the others are vacuous.
 class Forms;
-  rand bit [3:0]  mode;
-  rand bit [3:0]  a;
-  rand bit [3:0]  b;
-  rand bit [3:0]  c;
+  rand bit [3:0] mode;
+  rand bit [3:0] a;
+  rand bit [3:0] b;
+  rand bit [3:0] c;
   rand bit [31:0] address;
-  rand txn_e      txn_type;
-  rand bit [7:0]  arr [4];
-  rand bit [3:0]  uarr [3];
+  rand txn_e txn_type;
+  rand bit [7:0] arr [4];
+  rand bit [3:0] uarr [3];
 
   // Bare expression (legacy form, supported pre-PR via expr->expr).
   constraint c_expr {
@@ -131,9 +131,9 @@ class DisSoftBothArms;
 endclass
 
 module t;
-  Forms   obj;
+  Forms obj;
   DisSoft ds;
-  int     ok;
+  int ok;
 
   initial begin
     obj = new();

test_regress/t/t_constraint_inside_typedef_array.v

@@ -16,19 +16,19 @@ package pkg;
   typedef int_q alias_q;
 
   class Bundle;
-    int_q  q;
+    int_q q;
     int_da d;
     int_up u;
   endclass
 endpackage
 
-module t(/*AUTOARG*/);
+module t;
   import pkg::*;
 
   initial begin
     automatic Bundle b = new();
-    automatic int    t_l = 0;
-    automatic int    rv;
+    automatic int t_l = 0;
+    automatic int rv;
     automatic alias_q a = '{32'd1, 32'd2, 32'd3};
 
     b.q = '{32'd10, 32'd20, 32'd30};

test_regress/t/t_opt_balance_cats.v

@@ -9,7 +9,7 @@ module t(
   i0, o0,
   i1, o1
 );
-  localparam N = 2000; // Deliberately not multiple of 32
+  localparam N = 2000;  // Deliberately not multiple of 32
 
   input clk;
   wire clk;
@@ -22,7 +22,7 @@ module t(
   output o0;
   wire [N-1:0] o0;
 
-  for (genvar n = 0 ; n + 31 < N ; n += 32) begin
+  for (genvar n = 0; n + 31 < N; n += 32) begin
     assign o0[n+ 0 +: 1] = i0[(N-1-n)- 0 -: 1];
     assign o0[n+ 1 +: 1] = i0[(N-1-n)- 1 -: 1];
     assign o0[n+ 2 +: 2] = i0[(N-1-n)- 2 -: 2];
@@ -35,7 +35,7 @@ module t(
     assign o0[n+31 +: 1] = i0[(N-1-n)-31 -: 1];
   end
 
-  for (genvar n = N / 32 * 32; n < N ; ++n) begin
+  for (genvar n = N / 32 * 32; n < N; ++n) begin
     assign o0[n] = i0[N-1-n];
   end