Add NEWERSTD warning when using feature in newer language standard (#4168) (#4172).

docs/CONTRIBUTORS

@@ -29,6 +29,7 @@ Drew Taussig
 Driss Hafdi
 Edgar E. Iglesias
 Eric Rippey
+Ethan Sifferman
 Eyck Jentzsch
 Fan Shupei
 february cozzocrea

docs/guide/warnings.rst

@@ -972,6 +972,21 @@ List Of Warnings
    (neither :vlopt:`--timing` nor :vlopt:`--no-timing` option was provided).
 
 
+.. option:: NEWERSTD
+
+   Warns that a feature requires a newer standard of Verilog or SystemVerilog
+   than the one specified by the :vlopt:`--language` option. For example, unsized
+   unbased literals (`'0`, `'1`, `'z`, `'x`) require 1800-2005 or later.
+
+   To avoid this warning, use a Verilog or SystemVerilog standard that
+   supports the feature. Alternatively, modify your code to use a different
+   syntax that is supported by the Verilog/SystemVerilog standard specified
+   by the :vlopt:`--language` option.
+
+   Ignoring this warning will only suppress the lint check; it will
+   simulate correctly.
+
+
 .. option:: NOLATCH
 
    .. TODO better example

src/V3AstNodeExpr.h

@@ -975,6 +975,20 @@ public:
         , m_num(this, 1, on) {
         dtypeSetBit();
     }
+    class All0 {};
+    AstConst(FileLine* fl, All0)
+        : ASTGEN_SUPER_Const(fl)
+        , m_num(this, "'0") {
+        initWithNumber();
+        fl->warnOff(V3ErrorCode::NEWERSTD, true);
+    }
+    class All1 {};
+    AstConst(FileLine* fl, All1)
+        : ASTGEN_SUPER_Const(fl)
+        , m_num(this, "'1") {
+        initWithNumber();
+        fl->warnOff(V3ErrorCode::NEWERSTD, true);
+    }
     class Null {};
     AstConst(FileLine* fl, Null)
         : ASTGEN_SUPER_Const(fl)

src/V3Error.h

@@ -116,6 +116,7 @@ public:
         MODDUP,         // Duplicate module
         MULTIDRIVEN,    // Driven from multiple blocks
         MULTITOP,       // Multiple top level modules
+        NEWERSTD,       // Newer language standard required
         NOLATCH,        // No latch detected in always_latch block
         NULLPORT,       // Null port detected in module definition
         PINCONNECTEMPTY,// Cell pin connected by name with empty reference
@@ -195,7 +196,7 @@ public:
             "IMPERFECTSCH", "IMPLICIT", "IMPLICITSTATIC", "IMPORTSTAR", "IMPURE",
             "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE",
             "LATCH", "LITENDIAN", "MINTYPMAXDLY", "MODDUP",
-            "MULTIDRIVEN", "MULTITOP", "NOLATCH", "NULLPORT", "PINCONNECTEMPTY",
+            "MULTIDRIVEN", "MULTITOP", "NEWERSTD", "NOLATCH", "NULLPORT", "PINCONNECTEMPTY",
             "PINMISSING", "PINNOCONNECT",  "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE",
             "PROFOUTOFDATE", "PROTECTED", "RANDC", "REALCVT", "REDEFMACRO", "RISEFALLDLY",
             "SELRANGE", "SHORTREAL", "SPLITVAR", "STATICVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
@@ -233,9 +234,9 @@ public:
         return (m_e == ALWCOMBORDER || m_e == ASCRANGE || m_e == BSSPACE || m_e == CASEINCOMPLETE
                 || m_e == CASEOVERLAP || m_e == CASEWITHX || m_e == CASEX || m_e == CASTCONST
                 || m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT || m_e == IMPLICITSTATIC
-                || m_e == LATCH || m_e == PINMISSING || m_e == REALCVT || m_e == STATICVAR
-                || m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC || m_e == WIDTHEXPAND
-                || m_e == WIDTHXZEXPAND);
+                || m_e == LATCH || m_e == NEWERSTD || m_e == PINMISSING || m_e == REALCVT
+                || m_e == STATICVAR || m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC
+                || m_e == WIDTHEXPAND || m_e == WIDTHXZEXPAND);
     }
     // Warnings that are style only
     bool styleError() const VL_MT_SAFE {

src/V3Inst.cpp

@@ -517,10 +517,10 @@ public:
             // otherwise done
             if (pinVarp->direction() == VDirection::INPUT
                 && cellp->modp()->unconnectedDrive().isSetTrue()) {
-                pinp->exprp(new AstConst{pinp->fileline(), AstConst::StringToParse{}, "'1"});
+                pinp->exprp(new AstConst{pinp->fileline(), AstConst::All1{}});
             } else if (pinVarp->direction() == VDirection::INPUT
                        && cellp->modp()->unconnectedDrive().isSetFalse()) {
-                pinp->exprp(new AstConst{pinp->fileline(), AstConst::StringToParse{}, "'0"});
+                pinp->exprp(new AstConst{pinp->fileline(), AstConst::All0{}});
             } else {
                 return nullptr;
             }

src/V3LinkDot.cpp

@@ -3117,8 +3117,7 @@ private:
                         if (v3Global.opt.bboxSys()) {
                             AstNode* newp;
                             if (VN_IS(nodep, FuncRef)) {
-                                newp = new AstConst{nodep->fileline(), AstConst::StringToParse{},
-                                                    "'0"};
+                                newp = new AstConst{nodep->fileline(), AstConst::All0{}};
                             } else {
                                 AstNode* outp = nullptr;
                                 while (nodep->pinsp()) {

src/V3LinkParse.cpp

@@ -240,7 +240,10 @@ private:
         if (nodep->isGParam() && m_modp) m_modp->hasGParam(true);
         if (nodep->isParam() && !nodep->valuep()
             && nodep->fileline()->language() < V3LangCode::L1800_2009) {
-            nodep->v3error("Parameter requires default value, or use IEEE 1800-2009 or later.");
+            nodep->v3warn(
+                NEWERSTD,
+                "Parameter requires default value, or use IEEE 1800-2009 or later."
+            );
         }
         if (VN_IS(nodep->subDTypep(), ParseTypeDType)) {
             // It's a parameter type. Use a different node type for this.
@@ -329,6 +332,15 @@ private:
             }
         }
     }
+    void visit(AstConst* nodep) override {
+        if (nodep->num().autoExtend()
+            && nodep->fileline()->language() < V3LangCode::L1800_2005) {
+                nodep->v3warn(
+                    NEWERSTD,
+                    "Unbased unsized literals require IEEE 1800-2005 or later."
+                );
+        }
+    }
 
     void visit(AstAttrOf* nodep) override {
         cleanFileline(nodep);

src/V3ParseGrammar.cpp

@@ -87,7 +87,8 @@ AstArg* V3ParseGrammar::argWrapList(AstNodeExpr* nodep) {
 AstNode* V3ParseGrammar::createSupplyExpr(FileLine* fileline, const string& name, int value) {
     AstAssignW* assignp
         = new AstAssignW{fileline, new AstVarRef{fileline, name, VAccess::WRITE},
-                         new AstConst{fileline, AstConst::StringToParse{}, (value ? "'1" : "'0")}};
+                         value ? new AstConst{fileline, AstConst::All1{}}
+                         : new AstConst{fileline, AstConst::All0{}} };
     AstStrengthSpec* strengthSpecp
         = new AstStrengthSpec{fileline, VStrength::SUPPLY, VStrength::SUPPLY};
     assignp->strengthSpecp(strengthSpecp);

test_regress/t/t_gate_fdup.pl

@@ -13,5 +13,9 @@ scenarios(simulator => 1);
 compile(
     );
 
+lint(
+    verilator_flags2 => ["--language 1364-2005"]
+    );
+
 ok(1);
 1;

test_regress/t/t_number_v_bad.out

@@ -0,0 +1,21 @@
+%Warning-NEWERSTD: t/t_number_v_bad.v:11:25: Unbased unsized literals require IEEE 1800-2005 or later.
+   11 |     wire [127:0] FOO1 = '0;
+      |                         ^~
+                   ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest
+                   ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message.
+%Warning-NEWERSTD: t/t_number_v_bad.v:12:25: Unbased unsized literals require IEEE 1800-2005 or later.
+   12 |     wire [127:0] FOO2 = '1;
+      |                         ^~
+%Warning-NEWERSTD: t/t_number_v_bad.v:13:25: Unbased unsized literals require IEEE 1800-2005 or later.
+   13 |     wire [127:0] FOO3 = 'x;
+      |                         ^~
+%Warning-NEWERSTD: t/t_number_v_bad.v:14:25: Unbased unsized literals require IEEE 1800-2005 or later.
+   14 |     wire [127:0] FOO4 = 'X;
+      |                         ^~
+%Warning-NEWERSTD: t/t_number_v_bad.v:15:25: Unbased unsized literals require IEEE 1800-2005 or later.
+   15 |     wire [127:0] FOO5 = 'z;
+      |                         ^~
+%Warning-NEWERSTD: t/t_number_v_bad.v:16:25: Unbased unsized literals require IEEE 1800-2005 or later.
+   16 |     wire [127:0] FOO6 = 'Z;
+      |                         ^~
+%Error: Exiting due to

test_regress/t/t_number_v_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Ethan Sifferman and Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--language 1364-2005"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_number_v_bad.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Test of Verilog and SystemVerilog integer literal differences
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Ethan Sifferman.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+    // "unbased_unsized_literal" is SystemVerilog only
+    // Should fail with "NEWERSTD"
+    wire [127:0] FOO1 = '0;
+    wire [127:0] FOO2 = '1;
+    wire [127:0] FOO3 = 'x;
+    wire [127:0] FOO4 = 'X;
+    wire [127:0] FOO5 = 'z;
+    wire [127:0] FOO6 = 'Z;
+
+endmodule

test_regress/t/t_param_default_presv_bad.out

@@ -1,4 +1,10 @@
-%Error: t/t_param_default_bad.v:7:26: Parameter requires default value, or use IEEE 1800-2009 or later.
+%Warning-NEWERSTD: t/t_param_default_bad.v:7:26: Parameter requires default value, or use IEEE 1800-2009 or later.
+    7 | module m #(parameter int Foo);
+      |                          ^~~
+                   ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest
+                   ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message.
+%Error: t/t_param_default_bad.v:7:26: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'Foo'
+                                    : ... In instance t.foo
     7 | module m #(parameter int Foo);
       |                          ^~~
 %Error: Exiting due to

test_regress/t/t_strength_assignments_constants.pl

@@ -17,5 +17,9 @@ execute(
     check_finished => 1,
     );
 
+lint(
+    verilator_flags2 => ["--language 1364-2005"]
+    );
+
 ok(1);
 1;

test_regress/t/t_strength_assignments_constants.v

@@ -14,18 +14,18 @@ module t (/*AUTOARG*/);
    assign (strong0, strong1) b = 0;
 
    wire [1:0] c;
-   assign (weak0, supply1) c = '1;
-   assign (supply0, pull1) c = '1;
-   assign (strong0, strong1) c = '0;
+   assign (weak0, supply1) c = 2'b11;
+   assign (supply0, pull1) c = 2'b11;
+   assign (strong0, strong1) c = 0;
 
    supply0 d;
    assign (strong0, strong1) d = 1;
 
-   wire (supply0, supply1) e = 'z;
+   wire (supply0, supply1) e = 1'bz;
    assign (weak0, weak1) e = 1;
 
    always begin
-      if (a && !b && c === '1 && !d && e) begin
+      if (a && !b && c === 2'b11 && !d && e) begin
          $write("*-* All Finished *-*\n");
          $finish;
       end

test_regress/t/t_strength_highz.pl

@@ -11,6 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(vlt => 1);
 
 lint(
+    verilator_flags2 => ["--language 1364-2005"],
     fails => $Self->{vlt_all},
     expect_filename => $Self->{golden_filename},
     );

test_regress/t/t_wire_beh1364_bad.out

@@ -1,22 +1,22 @@
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
                                                : ... In instance t
-   25 |       w = '0;   
+   26 |       w = 0;
       |       ^
                     ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
                                                : ... In instance t
-   26 |       o = '0;   
+   27 |       o = 0;
       |       ^
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
                                                : ... In instance t
-   27 |       oa = '0;   
+   28 |       oa = 0;
       |       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo'
                                                : ... In instance t
-   28 |       wo = '0;   
+   29 |       wo = 0;
       |       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:30:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa'
                                                : ... In instance t
-   29 |       woa = '0;   
+   30 |       woa = 0;
       |       ^~~
 %Error: Exiting due to

test_regress/t/t_wire_beh1364_bad.v

@@ -22,16 +22,18 @@ module t (/*AUTOARG*/
    //output var [1:0] voa;
 
    initial begin
-      w = '0;  // Error
-      o = '0;  // Error
-      oa = '0;  // Error
-      wo = '0;  // Error
-      woa = '0;  // Error
-      r = '0;  // Not an error
-      ro = '0;  // Not an error
-      roa = '0;  // Not an error
-      //vo = '0;  // Not an error
-      //voa = '0;  // Not an error
+      // Error
+      w = 0;
+      o = 0;
+      oa = 0;
+      wo = 0;
+      woa = 0;
+      // Not an error
+      r = 0;
+      ro = 0;
+      roa = 0;
+      //vo = 0;
+      //voa = 0;
    end
 
 endmodule

test_regress/t/t_wire_behp1364_bad.out

@@ -1,14 +1,14 @@
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
                                                 : ... In instance t
-   23 |       w = '0;   
+   24 |       w = 0;
       |       ^
                     ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
                                                 : ... In instance t
-   24 |       o = '0;   
+   25 |       o = 0;
       |       ^
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
                                                 : ... In instance t
-   25 |       oa = '0;   
+   26 |       oa = 0;
       |       ^~
 %Error: Exiting due to

test_regress/t/t_wire_behp1364_bad.v

@@ -20,16 +20,18 @@ module t (
    reg  r;
 
    initial begin
-      w = '0;  // Error
-      o = '0;  // Error
-      oa = '0;  // Error
-      wo = '0;  // Error
-      woa = '0;  // Error
-      r = '0;  // Not an error
-      ro = '0;  // Not an error
-      roa = '0;  // Not an error
-      //vo = '0;  // Not an error
-      //voa = '0;  // Not an error
+      // Error
+      w = 0;
+      o = 0;
+      oa = 0;
+      wo = 0;
+      woa = 0;
+      // Not an error
+      r = 0;
+      ro = 0;
+      roa = 0;
+      //vo = 0;
+      //voa = 0;
    end
 
 endmodule