Tests: Improve warning coverage

src/V3EmitCFunc.cpp

@@ -256,8 +256,9 @@ void EmitCFunc::displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const
             return;  // LCOV_EXCL_LINE
         }
         if (argp->widthMin() > VL_VALUE_STRING_MAX_WIDTH) {
-            dispp->v3error("Exceeded limit of " + cvtToStr(VL_VALUE_STRING_MAX_WIDTH)
+            dispp->v3warn(E_UNSUPPORTED, "Unsupported: Exceeded limit of "
-                           + " bits for any $display-like arguments");
+                                             + cvtToStr(VL_VALUE_STRING_MAX_WIDTH)
+                                             + " bits for any $display-like arguments");
         }
         if (argp->widthMin() > 8 && fmtLetter == 'c') {
             // Technically legal, but surely not what the user intended.

test_regress/t/t_assert_always_unsup.out

@@ -0,0 +1,13 @@
+%Error-UNSUPPORTED: t/t_assert_always_unsup.v:21:7: Unsupported: always[] (in property expression)
+   21 |       always [2:5] a;
+      |       ^~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_assert_always_unsup.v:25:7: Unsupported: s_always (in property expression)
+   25 |       s_always [2:5] a;
+      |       ^~~~~~~~
+%Error: t/t_assert_always_unsup.v:29:20: syntax error, unexpected ':', expecting ']'
+   29 |       eventually [2:5] a;
+      |                    ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Cannot continue
+        ... This fatal error may be caused by the earlier error(s); resolve those first.

test_regress/t/t_assert_always_unsup.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True)
+
+test.passes()

test_regress/t/t_assert_always_unsup.v

@@ -0,0 +1,48 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   property p_alw;
+      always [2:5] a;
+   endproperty
+
+   property p_s_alw;
+      s_always [2:5] a;
+   endproperty
+
+   property p_ev;
+      eventually [2:5] a;
+   endproperty
+
+   property p_ev2;
+      eventually [2] a;
+   endproperty
+
+   property p_s_ev;
+      s_eventually [2:5] a;
+   endproperty
+
+   property p_s_alw_ev;
+      always s_eventually [2:5] a;
+   endproperty
+
+   property p_s_ev_alw;
+      s_eventually always [2:5] a;
+   endproperty
+
+endmodule

test_regress/t/t_c_width_bad.out

@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_c_width_bad.v:9:22: Unsupported: $c can't generate wider than 64 bits
+                                          : ... note: In instance 't'
+    9 |    bit [99:0] wide = $c100("0");
+      |                      ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_c_width_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_c_width_bad.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Test of select from constant
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   bit [99:0] wide = $c100("0");
+
+   initial $display("%d", wide);
+
+endmodule

test_regress/t/t_display_wide_bad.out

@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_display_wide_bad.v:25:10: Unsupported: Exceeded limit of 8192 bits for any $display-like arguments
+   25 |          $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc});   
+      |          ^~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_display_wide_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_display_wide_bad.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2011 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc = 0;
+   reg [4095:0] crc;
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]};  // not a good crc :)
+      if (cyc==0) begin
+         // Setup
+         crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc});  // Too wide
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule

test_regress/t/t_dist_warn_coverage.py

@@ -19,6 +19,9 @@ Suppressed = {}
 
 for s in [
         ' exited with ',  # Is hit; driver.py filters out
+        ' loading non-variable',  # Instead 'storing to parameter' or syntax error
+        '--pipe-filter: Can\'t pipe: ',  # Can't test
+        '--pipe-filter: fork failed: ',  # Can't test
         'Assigned pin is neither input nor output',  # Instead earlier error
         'Define missing argument \'',  # Instead get Define passed too many arguments
         'Define or directive not defined: `',  # Instead V3ParseImp will warn
@@ -26,17 +29,15 @@ for s in [
         'Enum ranges must be integral, per spec',  # Hard to hit
         'Expecting define formal arguments. Found: ',  # Instead define syntax error
         'Import package not found: ',  # Errors earlier, until future parser released
+        'Member selection of non-struct/union object \'',  # Instead dotted expression error or V3Link other
         'Return with return value isn\'t underneath a function',  # Hard to hit, get other bad return messages
         'Syntax error parsing real: \'',  # Instead can't lex the number
         'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ',  # Instead get syntax error
         'Unsupported: Ranges ignored in port-lists',  # Hard to hit
         'dynamic new() not expected in this context (expected under an assign)',  # Instead get syntax error
         # Not yet analyzed
-        ' loading non-variable',
         '--pipe-filter protocol error, unexpected: ',
         '--pipe-filter returned bad status',
-        '--pipe-filter: Can\'t pipe: ',
-        '--pipe-filter: fork failed: ',
         'Argument needed for string.',
         'Array initialization has too few elements, need element ',
         'Assignment pattern with no members',
@@ -44,7 +45,6 @@ for s in [
         'Can\'t read annotation file: ',
         'Can\'t resolve module reference: \'',
         'Can\'t write file: ',
-        'Exceeded limit of ',
         'Extern declaration\'s scope is not a defined class',
         'File not found: ',
         'Format to $display-like function must have constant format string',
@@ -52,7 +52,6 @@ for s in [
         'Illegal +: or -: select; type already selected, or bad dimension: ',
         'Illegal bit or array select; type already selected, or bad dimension: ',
         'Illegal range select; type already selected, or bad dimension: ',
-        'Member selection of non-struct/union object \'',
         'Modport item is not a function/task: ',
         'Modport item is not a variable: ',
         'Modport item not found: ',
@@ -67,7 +66,6 @@ for s in [
         'String of ',
         'Symbol matching ',
         'Unexpected connection to arrayed port',
-        'Unmatched brackets in variable substitution in file: ',
         'Unsized numbers/parameters not allowed in streams.',
         'Unsupported RHS tristate construct: ',
         'Unsupported or syntax error: Unsized range in instance or other declaration',
@@ -75,7 +73,6 @@ for s in [
         'Unsupported tristate construct (not in propagation graph): ',
         'Unsupported tristate port expression: ',
         'Unsupported: $bits for queue',
-        'Unsupported: $c can\'t generate wider than 64 bits',
         'Unsupported: &&& expression',
         'Unsupported: +%- range',
         'Unsupported: +/- range',
@@ -100,7 +97,6 @@ for s in [
         'Unsupported: [] dimensions',
         'Unsupported: \'default :/\' constraint',
         'Unsupported: \'{} .* patterns',
-        'Unsupported: always[] (in property expression)',
         'Unsupported: assertion items in clocking blocks',
         'Unsupported: don\'t know how to deal with ',
         'Unsupported: eventually[] (in property expression)',
@@ -110,11 +106,9 @@ for s in [
         'Unsupported: no_inline for tasks',
         'Unsupported: property port \'local\'',
         'Unsupported: repeat event control',
-        'Unsupported: s_always (in property expression)',
         'Unsupported: static cast to ',
         'Unsupported: super',
         'Unsupported: this.super',
-        'Unsupported: trireg',
         'Unsupported: with[] stream expression',
 ]:
     Suppressed[s] = True
@@ -183,7 +177,7 @@ def check():
     read_outputs()
 
     print("Number of suppressions = " + str(len(Suppressed)))
-    print("Coverage = %3.1f%%" % (100 - int(100 * len(Suppressed) / len(Messages))))
+    print("Coverage = %3.1f%%" % (100 - (100 * len(Suppressed) / len(Messages))))
     print()
 
     print("Checking for v3error/v3warn messages in sources without")

test_regress/t/t_flag_f_bad_getenvend.out

@@ -0,0 +1,2 @@
+%Error: Unmatched brackets in variable substitution in file: $(GETENV_NO_END_PAREN
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

test_regress/t/t_flag_f_bad_getenvend.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(v_flags2=["-f t/t_flag_f_bad_getenvend.vc"],
+          fails=True,
+          expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_flag_f_bad_getenvend.vc

@@ -0,0 +1 @@
+$(GETENV_NO_END_PAREN

test_regress/t/t_wire_trireg_unsup.out

@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:11:4: Unsupported: trireg
+   11 |    trireg unsup;
+      |    ^~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_wire_trireg_unsup.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_wire_trireg_unsup.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
+//
+// Simple bi-directional alias test.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   trireg unsup;
+
+endmodule