Fix display of streaming concat arguments

This commit is contained in:
Jaeuk Lee 2026-07-07 08:37:45 +09:00 committed by JAEUK LEE
parent a5f4d40901
commit 6303bc454a
5 changed files with 57 additions and 0 deletions

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@ -110,6 +110,7 @@ Ilya Barkov
Iru Cai
Ivan Vnučec
Iztok Jeras
Jaeuk Lee (이재욱)
Jake Merdich
Jakub Michalski
Jakub Wasilewski

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@ -1002,6 +1002,14 @@ class WidthVisitor final : public VNVisitor {
}
}
if (m_vup->final()) {
const AstNode* backp = nodep->backp();
if (VN_IS(backp, SFormatArg)) backp = backp->backp();
if (VN_IS(backp, SFormatF)) {
nodep->v3error(
"Streaming concatenation cannot be used in an implicitly cast context "
"(IEEE 1800-2023 11.4.17)\n"
<< nodep->warnMore() << "... Suggest use a cast");
}
if (!nodep->dtypep()->widthSized()) {
// See also error in V3Number
nodeForUnsizedWarning(nodep)->v3warn(

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@ -0,0 +1,17 @@
%Error: t/t_display_stream_bad.v:11:15: Streaming concatenation cannot be used in an implicitly cast context (IEEE 1800-2023 11.4.17)
: ... note: In instance 't'
: ... Suggest use a cast
11 | $display({<<{value}});
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_display_stream_bad.v:12:22: Streaming concatenation cannot be used in an implicitly cast context (IEEE 1800-2023 11.4.17)
: ... note: In instance 't'
: ... Suggest use a cast
12 | $display("%0d", {<<{value}});
| ^~
%Error: t/t_display_stream_bad.v:13:29: Streaming concatenation cannot be used in an implicitly cast context (IEEE 1800-2023 11.4.17)
: ... note: In instance 't'
: ... Suggest use a cast
13 | void'($sformatf("%0d", {<<{value}}));
| ^~
%Error: Exiting due to

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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(fails=True, expect_filename=test.golden_filename)
test.passes()

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@ -0,0 +1,15 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t;
int value = 1;
initial begin
$display({<<{value}});
$display("%0d", {<<{value}});
void'($sformatf("%0d", {<<{value}}));
end
endmodule