Fix interface array connections with non-zero low declaration index.

Changes

@@ -81,6 +81,7 @@ Verilator 5.037 devel
 * Fix variables declared in fork after taskify (#6126). [Kamil Rakoczy, Antmicro Ltd.]
 * Fix method calls without parenthesis (#6127). [Alex Solomatnikov]
 * Fix `pre_randomize`/`post_randomize` when no randomize (#6128). [Alex Solomatnikov]
+* Fix interface array connections with non-zero low declaration index.
 
 
 Verilator 5.036 2025-04-27

src/V3Inst.cpp

@@ -373,7 +373,7 @@ private:
                         "Unsupported: Non-constant index when passing interface to module");
                     return;
                 }
-                const string index = AstNode::encodeNumber(constp->toSInt());
+                const string index = AstNode::encodeNumber(constp->toSInt() + arrp->lo());
                 if (VN_IS(arrselp->fromp(), SliceSel))
                     arrselp->fromp()->v3error("Unsupported: interface slices");
                 const AstVarRef* const varrefp = VN_CAST(arrselp->fromp(), VarRef);
@@ -482,7 +482,7 @@ private:
                                       "Non-constant index in RHS interface array selection");
                 return;
             }
-            const string index = AstNode::encodeNumber(constp->toSInt());
+            const string index = AstNode::encodeNumber(constp->toSInt() + arrp->lo());
             const AstVarRef* const varrefp = VN_CAST(nodep->fromp(), VarRef);
             UASSERT_OBJ(varrefp, nodep, "No interface varref under array");
             AstVarXRef* const newp = new AstVarXRef{

test_regress/t/t_interface_array4.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()

test_regress/t/t_interface_array4.v

@@ -0,0 +1,53 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface Ifc;
+  logic req, grant;
+  logic [7:0] addr, data;
+endinterface
+
+class Cls;
+  virtual Ifc bus;
+  int m_i;
+  function new(virtual Ifc s, int i);
+    bus = s;
+    m_i = i;
+  endfunction
+  task request();
+    bus.req <= 1'b1;
+  endtask
+  task wait_for_bus();
+    @(posedge bus.grant);
+  endtask
+endclass
+
+module devA (Ifc s);
+endmodule
+module devB (Ifc s);
+endmodule
+
+module top;
+  Ifc s14[1:4] ();
+  devA a1 (s14[1]);
+  devB b1 (s14[2]);
+  devA a2 (s14[3]);
+  devB b2 (s14[4]);
+
+  Ifc s65[6:5] ();
+  devA a3 (s65[5]);
+  devB b3 (s65[6]);
+
+  initial begin
+    Cls t14[1:4];
+    Cls t65[6:5];
+    t14[1] = new(s14[1], 1);
+    t14[2] = new(s14[2], 2);
+    t14[3] = new(s14[3], 3);
+    t14[4] = new(s14[4], 4);
+    t65[5] = new(s65[5], 5);
+    t65[6] = new(s65[6], 6);
+  end
+endmodule