Fix whitespace

test_regress/t/t_forceable_unpacked.v

@@ -4,13 +4,16 @@
 // SPDX-FileCopyrightText: 2026 Nikolai Kumar
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define checkh(g,e) do if ((g) !==(e)) begin $write("%%Error: %s:%0d: got=%x exp=%x\n", `__FILE__,`__LINE__, (g),(e)); $stop; end while(0)
 
 `ifdef CMT
-  `define FORCEABLE /*verilator forceable*/
+ `define FORCEABLE /*verilator forceable*/
 `else
-  `define FORCEABLE
+ `define FORCEABLE
 `endif
+// verilog_format: on
+
 module t (input wire clk, output reg [31:0] cyc);
   initial cyc = 0;
   always @(posedge clk) cyc <= cyc + 1;