Fix shift by x, bug760.
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4a58e859a4
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@ -234,16 +234,19 @@ private:
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}
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bool operandHugeShiftL(AstNodeBiop* nodep) {
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return (nodep->rhsp()->castConst()
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&& !nodep->rhsp()->castConst()->num().isFourState()
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&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->width())
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&& isTPure(nodep->lhsp()));
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}
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bool operandHugeShiftR(AstNodeBiop* nodep) {
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return (nodep->rhsp()->castConst()
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&& !nodep->rhsp()->castConst()->num().isFourState()
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&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->lhsp()->width())
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&& isTPure(nodep->lhsp()));
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}
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bool operandIsTwo(AstNode* nodep) {
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return (nodep->castConst()
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&& !nodep->castConst()->num().isFourState()
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&& nodep->width() <= VL_QUADSIZE
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&& nodep->castConst()->toUQuad()==2);
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}
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@ -4,11 +4,14 @@
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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ign,
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// Inputs
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clk
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);
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input clk;
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output [31:0] ign;
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reg [31:0] right;
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reg [31:0] left;
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@ -16,6 +19,8 @@ module t (/*AUTOARG*/
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reg [63:0] qleft;
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reg [31:0] amt;
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assign ign = {31'h0, clk} >>> 4'bx; // bug760
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always @* begin
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right = 32'h819b018a >> amt;
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left = 32'h819b018a << amt;
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