Fix internal error after MSB < LSB error reported to user. [Stefan Thiede]

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1017 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -23,6 +23,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix missing test_v in install datadir. [Holger Waechtler]
 
+**** Fix internal error after MSB < LSB error reported to user. [Stefan Thiede]
+
 * Verilator 3.660 2008/03/23
 
 ***  Add support for hard-coding VERILATOR_ROOT etc in the executables,

src/V3Width.cpp

@@ -243,15 +243,11 @@ private:
 		while (huntbackp->backp()->castRange()) huntbackp=huntbackp->backp();
 		if (huntbackp->backp()->castVar()
 		    && huntbackp->backp()->castVar()->arraysp()==huntbackp) {
-		    AstNRelinker msbHandle;
-		    AstNRelinker lsbHandle;
-		    msbConstp->unlinkFrBack(&msbHandle);
-		    lsbConstp->unlinkFrBack(&lsbHandle);
-		    msbHandle.relink(lsbConstp);
-		    lsbHandle.relink(msbConstp);
 		} else {
 		    nodep->v3error("Unsupported: MSB < LSB of bit range: "<<msb<<"<"<<lsb);
 		}
+		// Correct it.
+		swap(msbConstp, lsbConstp);
 		int x=msb; msb=lsb; lsb=x;
 	    }
 	    int width = msb-lsb+1;
@@ -275,6 +271,10 @@ private:
 		&& nodep->msbConst() < nodep->lsbConst()) {
 		nodep->v3error("Unsupported: MSB < LSB of bit extract: "
 			       <<nodep->msbConst()<<"<"<<nodep->lsbConst());
+		width = (nodep->lsbConst() - nodep->msbConst() + 1);
+		nodep->width(width,width);
+		nodep->widthp()->replaceWith(new AstConst(nodep->widthp()->fileline(), 
+							  width));
 		nodep->lsbp()->replaceWith(new AstConst(nodep->lsbp()->fileline(), 0));
 	    }
 	    // We're extracting, so just make sure the expression is at least wide enough.
@@ -720,6 +720,14 @@ private:
     bool fixAutoExtend (AstNode*& nodepr, int expWidth);
     void fixWidthExtend (AstNode* nodep, int expWidth);
     void fixWidthReduce (AstNode* nodep, int expWidth);
+    void swap (AstNode* ap, AstNode* bp) {
+	AstNRelinker aHandle;
+	AstNRelinker bHandle;
+	ap->unlinkFrBack(&aHandle);
+	bp->unlinkFrBack(&bHandle);
+	aHandle.relink(bp);
+	bHandle.relink(ap);
+    }
 
 public:
     // CONSTUCTORS

test_regress/t/t_select_bad_msb.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -10,7 +10,8 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 compile (
 	 fails=>1,
 	 expect=>
-'%Error: t/t_select_bad_msb.v:\d+: Unsupported: MSB < LSB of bit extract.*
+'%Error: t/t_select_bad_msb.v:\d+: Unsupported: MSB < LSB of bit range: 0<22
+%Error: t/t_select_bad_msb.v:\d+: Unsupported: MSB < LSB of bit extract: 1<4
 %Error: Exiting due to.*',
 	 ) if $Last_Self->{v3};
 

test_regress/t/t_select_bad_msb.v

@@ -9,6 +9,7 @@ module t (clk);
 
    reg [43:0] mi;
    reg [3:0]  sel2;
+   reg [0:22] backwd;
 
    always @ (posedge clk) begin
       mi = 44'h123;