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synced 2026-10-06 01:54:01 +02:00
Add experimental --pipe-filter to filter all Verilog input.
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+3
-3
@@ -104,7 +104,7 @@ void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool i
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}
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// Preprocess into m_ppBuffer
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V3PreShell::preproc(fileline, modfilename, this);
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V3PreShell::preproc(fileline, modfilename, m_filterp, this);
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if (v3Global.opt.preprocOnly() || v3Global.opt.keepTempFiles()) {
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// Create output file with all the preprocessor output we buffered up
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@@ -151,8 +151,8 @@ void V3ParseImp::lexFile(const string& modname) {
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//======================================================================
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// V3Parse functions
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V3Parse::V3Parse(AstNetlist* rootp) {
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m_impp = new V3ParseImp (rootp);
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V3Parse::V3Parse(AstNetlist* rootp, V3InFilter* filterp) {
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m_impp = new V3ParseImp (rootp, filterp);
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}
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V3Parse::~V3Parse() {
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delete m_impp; m_impp = NULL;
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