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Add experimental --pipe-filter to filter all Verilog input.

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This commit is contained in:
Wilson Snyder
2010-01-20 07:15:51 -05:00
parent 28eb5b9bc4
commit 6196cf09ff
25 changed files with 555 additions and 42 deletions
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src/V3LinkCells.cpp
+7 -4
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@@ -96,6 +96,8 @@ private:
AstUser1InUse m_inuser1;
// STATE
V3InFilter* m_filterp; // Parser filter
// Below state needs to be preserved between each module call.
AstNodeModule* m_modp; // Current module
V3SymTable m_mods; // Symbol table of all module names
@@ -174,7 +176,7 @@ private:
AstNodeModule* modp = m_mods.findIdUpward(nodep->modName())->castNodeModule();
if (!modp) {
// Read-subfile
V3Parse parser (v3Global.rootp());
V3Parse parser (v3Global.rootp(), m_filterp);
parser.parseFile(nodep->fileline(), nodep->modName(), false);
V3Error::abortIfErrors();
// We've read new modules, grab new pointers to their names
@@ -269,7 +271,8 @@ private:
public:
// CONSTUCTORS
LinkCellsVisitor(AstNetlist* rootp) {
LinkCellsVisitor(AstNetlist* rootp, V3InFilter* filterp) {
m_filterp = filterp;
m_modp = NULL;
m_libVertexp = NULL;
m_topVertexp = NULL;
@@ -281,7 +284,7 @@ public:
//######################################################################
// Link class functions
void V3LinkCells::link(AstNetlist* rootp) {
void V3LinkCells::link(AstNetlist* rootp, V3InFilter* filterp) {
UINFO(4,__FUNCTION__<<": "<<endl);
LinkCellsVisitor visitor (rootp);
LinkCellsVisitor visitor (rootp, filterp);
}