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Tests: Improve randc tests

This commit is contained in:
Wilson Snyder 2023-05-07 15:08:44 -04:00
parent c2a524d80b
commit 6188083baa
8 changed files with 164 additions and 44 deletions
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12
test_regress/t/t_randc.out Normal file
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@ -0,0 +1,12 @@
%Warning-RANDC: t/t_randc.v:8:26: Unsupported: Converting 'randc' to 'rand'
8 | randc bit [WIDTH-1:0] m_var;
| ^~~~~
... For warning description see https://verilator.org/warn/RANDC?v=latest
... Use "/* verilator lint_off RANDC */" and lint_on around source to disable this message.
%Warning-RANDC: t/t_randc.v:45:26: Unsupported: Converting 'randc' to 'rand'
45 | randc bit [WIDTH-1:0] m_var;
| ^~~~~
%Warning-RANDC: t/t_randc.v:74:17: Unsupported: Converting 'randc' to 'rand'
74 | randc enum_t m_var;
| ^~~~~
%Error: Exiting due to

19
test_regress/t/t_randc.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2020 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

125
test_regress/t/t_randc.v Normal file
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@ -0,0 +1,125 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class ClsNarrow #(parameter int WIDTH);
randc bit [WIDTH-1:0] m_var;
function void test;
automatic int i;
automatic int count[2**WIDTH];
automatic int maxcount;
automatic bit bad;
automatic int randomize_result;
for (int trial = 0; trial < 10; ++trial) begin
for (i = 0; i < (2 ** WIDTH); ++i) begin
randomize_result = randomize();
if (randomize_result !== 1) $stop;
`ifdef TEST_VERBOSE
$display("w%0d trial=%0d m_var=%0d", WIDTH, i, m_var);
`endif
++count[m_var];
end
end
maxcount = count[0];
bad = '0;
`ifndef TEST_IGNORE_RANDC
for (i = 0; i < (2 ** WIDTH); ++i) begin
if (maxcount != count[i]) bad = '1;
end
`endif
if (bad) begin
$display("%%Error: count mismatch");
for (i = 0; i < (2 ** WIDTH); ++i) begin
$display("w%0d entry[%0d]=%0d", WIDTH, i, count[i]);
end
$stop;
end
endfunction
endclass
class ClsWide #(parameter int WIDTH);
randc bit [WIDTH-1:0] m_var;
function void test;
automatic bit [WIDTH-1:0] last;
automatic int randomize_result;
for (int i = 0; i < 100; ++i) begin
randomize_result = randomize();
if (randomize_result !== 1) $stop;
`ifdef TEST_VERBOSE
$display("ww%0d m_var=%0d", WIDTH, i, m_var);
`endif
if (i != 0) begin
`ifndef TEST_IGNORE_RANDC
if (m_var == last) $stop;
`endif
end
last = m_var;
end
endfunction
endclass
class ClsEnum;
typedef enum bit [3:0] {
TWO = 2,
FIVE = 5,
SIX = 6
} enum_t;
randc enum_t m_var;
function void test;
automatic enum_t last;
automatic int randomize_result;
for (int trial = 0; trial < 10; ++trial) begin
for (int i = 0; i < 3; ++i) begin
randomize_result = randomize();
if (randomize_result !== 1) $stop;
`ifdef TEST_VERBOSE
$display("we trial=%0d m_var=%0d", i, m_var);
`endif
if (m_var != TWO && m_var != FIVE && m_var != SIX) $stop;
if (i != 0) begin
`ifndef TEST_IGNORE_RANDC
if (m_var == last) $stop;
`endif
end
last = m_var;
end
end
endfunction
endclass
module t (/*AUTOARG*/);
ClsNarrow #(1) c1; // Degenerate case
ClsNarrow #(2) c2;
ClsNarrow #(9) c9;
ClsWide #(31) c31;
ClsWide #(32) c32;
ClsEnum ce;
initial begin
c1 = new;
c1.test();
c2 = new;
c2.test();
c9 = new;
c9.test();
c31 = new;
c31.test();
c32 = new;
c32.test();
ce = new;
ce.test();
$write("*-* All Finished *-*\n");
$finish();
end
endmodule

4
test_regress/t/t_randc_ignore_unsup.pl
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@ -10,8 +10,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
top_filename("t/t_randc.v");
compile(
verilator_flags2 => ['-Wno-RANDC'],
verilator_flags2 => ['-Wno-RANDC -DTEST_IGNORE_RANDC'],
);
execute(

38
test_regress/t/t_randc_ignore_unsup.v
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@ -1,38 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Cls;
randc int i;
function new;
i = 0;
endfunction
endclass
module t (/*AUTOARG*/);
bit ok = 0;
Cls obj;
initial begin
int rand_result;
int prev_i;
for (int i = 0; i < 10; i++) begin
obj = new;
rand_result = obj.randomize();
if (i > 0 && obj.i != prev_i) begin
ok = 1;
end
prev_i = obj.i;
end
if (ok) begin
$write("*-* All Finished *-*\n");
$finish;
end
else $stop;
end
endmodule

6
test_regress/t/t_randc_unsup.out → test_regress/t/t_randc_oversize_bad.out
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@ -1,6 +1,6 @@
%Warning-RANDC: t/t_randc_unsup.v:8:14: Unsupported: Converting 'randc' to 'rand'
8 | randc int i;
| ^
%Warning-RANDC: t/t_randc_oversize_bad.v:8:21: Unsupported: Converting 'randc' to 'rand'
8 | randc bit [33:0] i;
| ^
... For warning description see https://verilator.org/warn/RANDC?v=latest
... Use "/* verilator lint_off RANDC */" and lint_on around source to disable this message.
%Error: Exiting due to

0
test_regress/t/t_randc_unsup.pl → test_regress/t/t_randc_oversize_bad.pl
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4
test_regress/t/t_randc_unsup.v → test_regress/t/t_randc_oversize_bad.v
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@ -1,11 +1,11 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Cls;
randc int i;
randc bit [33:0] i;
endclass
module t (/*AUTOARG*/);