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Fix Verilog coverage to pass real column information

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This commit is contained in:
Wilson Snyder
2020-05-31 09:05:10 -04:00
parent 047852eb08
commit 611e8b10c6
3 changed files with 18 additions and 20 deletions
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src/V3EmitC.cpp
+1 -1
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@@ -400,7 +400,7 @@ public:
puts(", ");
puts(cvtToStr(nodep->fileline()->lineno()));
puts(", ");
puts(cvtToStr(nodep->column()));
puts(cvtToStr(nodep->fileline()->firstColumn()));
puts(", ");
putsQuoted((!nodep->hier().empty() ? "." : "")
+ protectWordsIf(nodep->hier(), nodep->protect()));