Fix 'case (_) inside' with x wildcards (#7766)
Found by inspection, case inside used to threat 'x' as a value, not as a wildcard. Per the standard it should behave as '==?' which treats both 'x' and 'z' as wildcards.
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@ -576,8 +576,8 @@ class CaseVisitor final : public VNVisitor {
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bool neverItem(const AstCase* casep, const AstConst* itemp) {
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// Xs in case or casez are impossible due to two state simulations
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if (casep->casex()) {
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} else if (casep->casez() || casep->caseInside()) {
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if (casep->casex() || casep->caseInside()) {
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} else if (casep->casez()) {
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if (itemp->num().isAnyX()) return true;
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} else {
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if (itemp->num().isFourState()) return true;
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,35 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module top;
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bit clk = 1'b0;
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always #1 clk = ~clk;
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logic [2:0] cyc = 3'd0;
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int count = 0;
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always @(posedge clk) begin
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// verilator lint_off CASEWITHX
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case (cyc) inside
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3'b000: begin $display("case inside 000"); ++count; end
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3'b001: begin $display("case inside 001"); ++count; end
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// Should match z
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3'b01?: begin $display("case inside 01?"); ++count; end
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// Should match x
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3'b1xx: begin $display("case inside 1xx"); ++count; end
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endcase
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// verilator lint_on CASEWITHX
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cyc <= cyc + 3'd1;
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if (&cyc) begin
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`checkh(count, 8);
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$finish;
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end
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end
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endmodule
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