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https://github.com/verilator/verilator.git
synced 2026-10-06 18:13:50 +02:00
Internals: Favor std::swap. No functional change.
This commit is contained in:
+7
-21
@@ -448,21 +448,15 @@ class WidthSelVisitor final : public VNVisitor {
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adtypep,
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"Array extraction with width miscomputed " << adtypep->width() << "/"
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<< fromRange.elements());
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if (fromRange.ascending()) {
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// Below code assumes descending bit range; just works out if we swap
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const int x = msb;
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msb = lsb;
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lsb = x;
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}
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// Below code assumes descending bit range; just works out if we swap
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if (fromRange.ascending()) std::swap(msb, lsb);
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if (lsb > msb) {
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nodep->v3warn(
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SELRANGE,
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"[" << msb << ":" << lsb
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<< "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb
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<< ":" << msb << "]");
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const int x = msb;
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msb = lsb;
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lsb = x;
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std::swap(msb, lsb);
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}
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const int elwidth = adtypep->width() / fromRange.elements();
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AstSel* const newp
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@@ -477,21 +471,15 @@ class WidthSelVisitor final : public VNVisitor {
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nodep->replaceWith(newp);
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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} else if (VN_IS(ddtypep, BasicDType)) {
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if (fromRange.ascending()) {
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// Below code assumes descending bit range; just works out if we swap
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const int x = msb;
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msb = lsb;
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lsb = x;
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}
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// Below code assumes descending bit range; just works out if we swap
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if (fromRange.ascending()) std::swap(msb, lsb);
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if (lsb > msb) {
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nodep->v3warn(
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SELRANGE,
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"[" << msb << ":" << lsb
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<< "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb
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<< ":" << msb << "]");
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const int x = msb;
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msb = lsb;
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lsb = x;
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std::swap(msb, lsb);
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}
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AstSel* const newp = new AstSel{nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange),
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msb + 1 - lsb};
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@@ -508,9 +496,7 @@ class WidthSelVisitor final : public VNVisitor {
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"[" << msb << ":" << lsb
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<< "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb
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<< ":" << msb << "]");
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const int x = msb;
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msb = lsb;
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lsb = x;
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std::swap(msb, lsb);
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}
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AstSel* const newp = new AstSel{nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange),
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msb + 1 - lsb};
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