Fix imports under multiple instantiated cells, bug542.
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@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix double-deep parameter cell WIDTHs, bug541. [Hiroki Honda]
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**** Fix imports under multiple instantiated cells, bug542. [Alex Solomatnikov]
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**** Fix defparam in generate broke in 3.840, bug543. [Alex Solomatnikov]
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@ -743,8 +743,7 @@ private:
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}
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}
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m_curSymp->import(srcp, nodep->name());
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// No longer needed
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nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
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// No longer needed, but can't delete until any multi-instantiated modules are expanded
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}
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virtual void visit(AstNode* nodep, AstNUser*) {
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@ -1297,6 +1296,7 @@ private:
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<<"'"<<" as a "<<foundp->nodep()->typeName()
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<<" but expected a "<<expectWhat);
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} else if (m_dotText=="") {
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UINFO(7," ErrParseRef curSymp=se"<<(void*)m_curSymp<<" dotSymp=se"<<(void*)m_dotSymp<<endl);
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nodep->v3error("Can't find definition of "<<expectWhat
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<<": "<<nodep->prettyName());
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} else {
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@ -1445,7 +1445,9 @@ private:
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nodep->packagep(foundp->packagep());
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UINFO(7," Resolved "<<nodep<<endl); // Also prints taskp
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} else {
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// Note ParseRef has similar error handling/message output
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m_statep->preErrorDump();
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UINFO(7," ErrFtask curSymp=se"<<(void*)m_curSymp<<" dotSymp=se"<<(void*)dotSymp<<endl);
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if (nodep->dotted() == "") {
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nodep->v3error("Can't find definition of task/function: "<<nodep->prettyName());
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} else {
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@ -1527,6 +1529,10 @@ private:
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}
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nodep->unlinkFrBack()->deleteTree();
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}
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virtual void visit(AstPackageImport* nodep, AstNUser*) {
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// No longer needed
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nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
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}
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virtual void visit(AstNode* nodep, AstNUser*) {
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// Default: Just iterate
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nodep->iterateChildren(*this);
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@ -0,0 +1,16 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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# Compile only
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ok(1);
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1;
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@ -0,0 +1,68 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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package defs;
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function automatic integer max;
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input integer a;
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input integer b;
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max = (a > b) ? a : b;
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endfunction
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function automatic integer log2;
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input integer value;
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value = value >> 1;
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for (log2 = 0; value > 0; log2 = log2 + 1)
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value = value >> 1;
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endfunction
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function automatic integer ceil_log2;
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input integer value;
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value = value - 1;
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for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
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value = value >> 1;
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endfunction
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endpackage
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module sub();
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import defs::*;
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parameter RAND_NUM_MAX = "";
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localparam DATA_RANGE = RAND_NUM_MAX + 1;
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localparam DATA_WIDTH = ceil_log2(DATA_RANGE);
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localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1));
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endmodule
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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import defs::*;
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parameter WHICH = 0;
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parameter MAX_COUNT = 10;
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localparam MAX_EXPONENT = log2(MAX_COUNT);
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localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1);
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input clk;
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generate
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if (WHICH == 1)
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begin : which_true
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sub sub_true();
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defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT;
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end
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else
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begin : which_false
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sub sub_false();
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defparam sub_false.RAND_NUM_MAX = MAX_COUNT;
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end
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endgenerate
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endmodule
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