Fix imports under multiple instantiated cells, bug542.

This commit is contained in:
Wilson Snyder 2012-08-08 21:59:17 -04:00
parent 923efa004b
commit 5f9810070d
4 changed files with 94 additions and 2 deletions

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@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix double-deep parameter cell WIDTHs, bug541. [Hiroki Honda]
**** Fix imports under multiple instantiated cells, bug542. [Alex Solomatnikov]
**** Fix defparam in generate broke in 3.840, bug543. [Alex Solomatnikov]

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@ -743,8 +743,7 @@ private:
}
}
m_curSymp->import(srcp, nodep->name());
// No longer needed
nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
// No longer needed, but can't delete until any multi-instantiated modules are expanded
}
virtual void visit(AstNode* nodep, AstNUser*) {
@ -1297,6 +1296,7 @@ private:
<<"'"<<" as a "<<foundp->nodep()->typeName()
<<" but expected a "<<expectWhat);
} else if (m_dotText=="") {
UINFO(7," ErrParseRef curSymp=se"<<(void*)m_curSymp<<" dotSymp=se"<<(void*)m_dotSymp<<endl);
nodep->v3error("Can't find definition of "<<expectWhat
<<": "<<nodep->prettyName());
} else {
@ -1445,7 +1445,9 @@ private:
nodep->packagep(foundp->packagep());
UINFO(7," Resolved "<<nodep<<endl); // Also prints taskp
} else {
// Note ParseRef has similar error handling/message output
m_statep->preErrorDump();
UINFO(7," ErrFtask curSymp=se"<<(void*)m_curSymp<<" dotSymp=se"<<(void*)dotSymp<<endl);
if (nodep->dotted() == "") {
nodep->v3error("Can't find definition of task/function: "<<nodep->prettyName());
} else {
@ -1527,6 +1529,10 @@ private:
}
nodep->unlinkFrBack()->deleteTree();
}
virtual void visit(AstPackageImport* nodep, AstNUser*) {
// No longer needed
nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
}
virtual void visit(AstNode* nodep, AstNUser*) {
// Default: Just iterate
nodep->iterateChildren(*this);

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@ -0,0 +1,16 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
# Compile only
ok(1);
1;

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@ -0,0 +1,68 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
package defs;
function automatic integer max;
input integer a;
input integer b;
max = (a > b) ? a : b;
endfunction
function automatic integer log2;
input integer value;
value = value >> 1;
for (log2 = 0; value > 0; log2 = log2 + 1)
value = value >> 1;
endfunction
function automatic integer ceil_log2;
input integer value;
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
endfunction
endpackage
module sub();
import defs::*;
parameter RAND_NUM_MAX = "";
localparam DATA_RANGE = RAND_NUM_MAX + 1;
localparam DATA_WIDTH = ceil_log2(DATA_RANGE);
localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1));
endmodule
module t(/*AUTOARG*/
// Inputs
clk
);
import defs::*;
parameter WHICH = 0;
parameter MAX_COUNT = 10;
localparam MAX_EXPONENT = log2(MAX_COUNT);
localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1);
input clk;
generate
if (WHICH == 1)
begin : which_true
sub sub_true();
defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT;
end
else
begin : which_false
sub sub_false();
defparam sub_false.RAND_NUM_MAX = MAX_COUNT;
end
endgenerate
endmodule