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Internals: Use width when widthMin is the same. No functional change intended

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This commit is contained in:
Wilson Snyder
2011-12-22 21:10:28 -05:00
parent b32f925468
commit 5e81543448
8 changed files with 24 additions and 16 deletions
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src/V3Task.cpp
+3 -3
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@@ -621,13 +621,13 @@ private:
stmt += "VL_CVT_VP_Q(";
ket += ")";
}
else if (portp->basicp() && portp->basicp()->isBitLogic() && portp->widthMin() != 1 && portp->isQuad()) {
else if (portp->basicp() && portp->basicp()->isBitLogic() && portp->width() != 1 && portp->isQuad()) {
// SV is vector, Verilator isn't
stmt += "VL_SET_QW(";
ket += ")";
}
if (!cvt
&& portp->basicp() && portp->basicp()->isBitLogic() && portp->widthMin() != 1 && !portp->isWide() && !portp->isQuad())
&& portp->basicp() && portp->basicp()->isBitLogic() && portp->width() != 1 && !portp->isWide() && !portp->isQuad())
stmt += "*"; // it's a svBitVecVal, which other code won't think is arrayed (as WData aren't), but really is
stmt += frName;
stmt += ket;
@@ -778,7 +778,7 @@ private:
if (args != "") { args+= ", "; }
if (bitvec) {}
else if (portp->isOutput()) args += "&";
else if (portp->basicp() && portp->basicp()->isBitLogic() && portp->widthMin() != 1) args += "&"; // it's a svBitVecVal
else if (portp->basicp() && portp->basicp()->isBitLogic() && portp->width() != 1) args += "&"; // it's a svBitVecVal
args += portp->name()+"__Vcvt";