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IEEE compliant scheduler (#3384)
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
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+6
-5
@@ -1056,17 +1056,18 @@ private:
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}
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AstVarScope* makeDpiExporTrigger() {
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AstVarScope* dpiExportTriggerp = v3Global.rootp()->dpiExportTriggerp();
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AstNetlist* const netlistp = v3Global.rootp();
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AstVarScope* dpiExportTriggerp = netlistp->dpiExportTriggerp();
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if (!dpiExportTriggerp) {
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// Create the global DPI export trigger flag the first time we encounter a DPI export.
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// This flag is set any time a DPI export is invoked, and cleared at the end of eval.
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FileLine* const fl = m_topScopep->fileline();
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AstVar* const varp
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= new AstVar{fl, VVarType::VAR, "__Vdpi_export_trigger", VFlagBitPacked{}, 1};
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const string name{"__Vdpi_export_trigger"};
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AstVar* const varp = new AstVar{fl, VVarType::VAR, name, VFlagBitPacked{}, 1};
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m_topScopep->scopep()->modp()->addStmtp(varp);
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dpiExportTriggerp = new AstVarScope{fl, m_topScopep->scopep(), varp};
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m_topScopep->scopep()->addVarp(dpiExportTriggerp);
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v3Global.rootp()->dpiExportTriggerp(dpiExportTriggerp);
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netlistp->dpiExportTriggerp(dpiExportTriggerp);
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}
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return dpiExportTriggerp;
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}
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@@ -1309,7 +1310,7 @@ private:
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AstAlways* const alwaysp = new AstAlways{
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fl, VAlwaysKwd::ALWAYS,
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new AstSenTree{
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fl, new AstSenItem{fl, VEdgeType::ET_HIGHEDGE,
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fl, new AstSenItem{fl, VEdgeType::ET_DPIEXPORT,
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new AstVarRef{fl, dpiExportTriggerp, VAccess::READ}}},
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nullptr};
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for (AstVarScope* const varScopep : writtenps) {
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