IEEE compliant scheduler (#3384)

This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278

src/V3LinkLValue.cpp

@@ -92,6 +92,13 @@ private:
             iterateAndNextNull(nodep->lhsp());
         }
     }
+    virtual void visit(AstFireEvent* nodep) override {
+        VL_RESTORER(m_setRefLvalue);
+        {
+            m_setRefLvalue = VAccess::WRITE;
+            iterateAndNextNull(nodep->operandp());
+        }
+    }
     virtual void visit(AstCastDynamic* nodep) override {
         VL_RESTORER(m_setRefLvalue);
         {