IEEE compliant scheduler (#3384)

This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278

src/V3CCtors.cpp

@@ -185,7 +185,9 @@ void V3CCtors::cctorsAll() {
             for (AstNode* np = modp->stmtsp(); np; np = np->nextp()) {
                 if (AstVar* const varp = VN_CAST(np, Var)) {
                     if (!varp->isIfaceParent() && !varp->isIfaceRef() && !varp->noReset()
-                        && !varp->isParam()) {
+                        && !varp->isParam()
+                        && !(varp->basicp()
+                             && (varp->basicp()->isEvent() || varp->basicp()->isTriggerVec()))) {
                         const auto vrefp = new AstVarRef{varp->fileline(), varp, VAccess::WRITE};
                         var_reset.add(new AstCReset{varp->fileline(), vrefp});
                     }