Fix duplicate std:: declaration with -I (#4215).

Changes

@@ -31,6 +31,7 @@ Verilator 5.011 devel
 * Fix arrays of unpacked structs (#4173). [Risto Pejašinović]
 * Fix $fscanf of decimals overflowing variables (#4174). [Ahmed El-Mahmoudy]
 * Fix super.new missing data type (#4147). [Tudor Timi]
+* Fix duplicate std:: declaration with -I (#4215). [Harald Pretl]
 * Fix detection of wire/reg duplicates.
 * Fix false IMPLICITSTATIC on package functions.
 

src/V3Options.cpp

@@ -547,6 +547,11 @@ string V3Options::filePath(FileLine* fl, const string& modname, const string& la
     // Find a filename to read the specified module name,
     // using the incdir and libext's.
     // Return "" if not found.
+    if (modname[0] == '/') {
+        // If leading /, obey existing absolute path, so can find getStdPackagePath()
+        string exists = filePathCheckOneDir(modname, "");
+        if (exists != "") return exists;
+    }
     for (const string& dir : m_impp->m_incDirUsers) {
         string exists = filePathCheckOneDir(modname, dir);
         if (exists != "") return exists;

src/V3Os.cpp

@@ -126,7 +126,7 @@ void V3Os::setenvStr(const string& envvar, const string& value, const string& wh
 
 string V3Os::filenameFromDirBase(const string& dir, const string& basename) {
     // Don't return ./{filename} because if filename was absolute, that makes it relative
-    if (dir == ".") {
+    if (dir.empty() || dir == ".") {
         return basename;
     } else {
         return dir + "/" + basename;

test_regress/t/t_flag_i_empty.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["-Wno-MODDUP -I t_flag_i_empty.v t_flag_i_empty.v"],
+    );
+
+ok(1);
+1;

test_regress/t/t_flag_i_empty.v

@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2016 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+endmodule