mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 10:03:44 +02:00
Fix internals to make null-pointer-check clean. Also add more const's. No functional change intended, but likely something will break.
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+13
-13
@@ -270,7 +270,7 @@ private:
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virtual void visit(AstNodeAssign* nodep) {
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m_hasClk = false;
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if (AstVarRef* varrefp = nodep->rhsp()->castVarRef()) {
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if (AstVarRef* varrefp = VN_CAST(nodep->rhsp(), VarRef)) {
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this->visit(varrefp);
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m_rightClkWidth = varrefp->width();
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if (varrefp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
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@@ -298,7 +298,7 @@ private:
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return; // skip the marking
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}
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AstVarRef* lhsp = nodep->lhsp()->castVarRef();
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const AstVarRef* lhsp = VN_CAST(nodep->lhsp(), VarRef);
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if (lhsp && (lhsp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_UNKNOWN)) {
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lhsp->varp()->attrClocker(AstVarAttrClocker::CLOCKER_YES); // mark as clocker
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m_newClkMarked = true; // enable a further run since new clocker is marked
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@@ -343,8 +343,8 @@ private:
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virtual void visit(AstReplicate* nodep) {
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if (m_inAss) {
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nodep->iterateChildren(*this);
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if (nodep->rhsp()->castConst()) {
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m_childClkWidth = m_childClkWidth * nodep->rhsp()->castConst()->toUInt();
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if (VN_IS(nodep->rhsp(), Const)) {
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m_childClkWidth = m_childClkWidth * VN_CAST(nodep->rhsp(), Const)->toUInt();
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} else {
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m_childClkWidth = nodep->width(); // can not check in this case.
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}
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@@ -389,7 +389,7 @@ private:
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return level;
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}
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virtual void visit(AstNodeAssign* nodep) {
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if (AstVarRef* varrefp = nodep->lhsp()->castVarRef() )
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if (const AstVarRef* varrefp = VN_CAST(nodep->lhsp(), VarRef) )
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if (varrefp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
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m_clkAss = true;
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UINFO(6, "node was marked as clocker "<<varrefp<<endl);
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@@ -563,8 +563,8 @@ private:
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toLVtxp = dynamic_cast<OrderLogicVertex*>(edgep->top());
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}
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//
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if ((fromLVtxp && fromLVtxp->nodep()->castInitial())
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|| (toLVtxp && toLVtxp->nodep()->castInitial())) {
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if ((fromLVtxp && VN_IS(fromLVtxp->nodep(), Initial))
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|| (toLVtxp && VN_IS(toLVtxp->nodep(), Initial))) {
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// IEEE does not specify ordering between initial blocks, so we can do whatever we want
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// We especially do not want to evaluate multiple times, so do not mark the edge circular
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}
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@@ -1079,7 +1079,7 @@ void OrderVisitor::processInputsOutIterate(OrderEitherVertex* vertexp, VertexVec
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processInputsInIterate(vvertexp, todoVec);
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}
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if (OrderLogicVertex* vvertexp = dynamic_cast<OrderLogicVertex*>(toVertexp)) {
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if (vvertexp->nodep()->castNodeAssign()) {
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if (VN_IS(vvertexp->nodep(), NodeAssign)) {
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processInputsInIterate(vvertexp, todoVec);
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}
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}
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@@ -1340,8 +1340,8 @@ bool OrderVisitor::domainsExclusive(const AstSenTree* fromp,
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// always @(negedge A)
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//
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// ... unless you know more about A and B, which sounds hard.
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const AstSenItem* fromSenListp = fromp->sensesp()->castSenItem();
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const AstSenItem* toSenListp = top->sensesp()->castSenItem();
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const AstSenItem* fromSenListp = VN_CAST(fromp->sensesp(), SenItem);
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const AstSenItem* toSenListp = VN_CAST(top->sensesp(), SenItem);
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// If clk gating is ever reenabled, we may need to update this to handle
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// AstSenGate also.
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if (!fromSenListp) fromp->v3fatalSrc("sensitivity list item is not an AstSenItem");
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@@ -1516,11 +1516,11 @@ void OrderVisitor::processMoveOne(OrderMoveVertex* vertexp, OrderMoveDomScope* d
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<<" s="<<(void*)(scopep)<<" "<<lvertexp<<endl);
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AstSenTree* domainp = lvertexp->domainp();
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AstNode* nodep = lvertexp->nodep();
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AstNodeModule* modp = scopep->user1p()->castNodeModule(); UASSERT(modp,"NULL"); // Stashed by visitor func
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if (nodep->castUntilStable()) {
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AstNodeModule* modp = VN_CAST(scopep->user1p(), NodeModule); UASSERT(modp,"NULL"); // Stashed by visitor func
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if (VN_IS(nodep, UntilStable)) {
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nodep->v3fatalSrc("Not implemented");
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}
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else if (nodep->castSenTree()) {
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else if (VN_IS(nodep, SenTree)) {
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// Just ignore sensitivities, we'll deal with them when we move statements that need them
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}
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else { // Normal logic
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