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[#73220] remove unnecessary test files

This commit is contained in:
Mateusz Gancarz 2025-02-26 08:36:58 +01:00
parent 47eb7e0eda
commit 589b462a0a
9 changed files with 0 additions and 883 deletions
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21
test_regress/t/saif_tests/t_trace_event_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_event.v"
test.compile(verilator_flags2=['--trace-saif --binary'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

20
test_regress/t/saif_tests/t_trace_saif_cmake.py
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@ -1,20 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.compile(v_flags2=["--trace-saif"], verilator_make_gmake=False, verilator_make_cmake=1)
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

19
test_regress/t/saif_tests/t_trace_string_saif.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_string.v"
test.compile(verilator_flags2=['--cc --trace-saif'])
test.execute()
test.passes()

38
test_regress/t/saif_tests/t_trace_two_dumpsaif_cc.py
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@ -1,38 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# Test tracing with two models instanced
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t_trace_two_a.v"
test.compile(make_main=False,
verilator_make_gmake=False,
top_filename='t_trace_two_b.v',
vm_prefix='Vt_trace_two_b',
verilator_flags2=['--trace-saif --trace-threads 1 -DTEST_FST'])
test.run(logfile=test.obj_dir + "/make_first_ALL.log",
cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"])
test.compile(make_main=False,
top_filename='t_trace_two_a.v',
verilator_flags2=[
'-exe', '--trace-saif --trace-threads 1', '-DTEST_FST',
test.t_dir + "/t_trace_two_cc.cpp"
],
v_flags2=['+define+TEST_DUMP'])
test.execute()
if test.vlt_all:
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

39
test_regress/t/saif_tests/t_trace_two_hdrsaif_cc.py
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@ -1,39 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# Test tracing with two models instanced
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t_trace_two_a.v"
test.compile(make_main=False,
verilator_make_gmake=False,
top_filename='t_trace_two_b.v',
vm_prefix='Vt_trace_two_b',
verilator_flags2=['--trace-saif --trace-threads 1'])
test.run(
logfile=test.obj_dir + "/make_first_ALL.log",
cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"])
test.compile(make_main=False,
top_filename='t_trace_two_a.v',
make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'],
verilator_flags2=[
'-exe', '--trace-saif --trace-threads 1', '-DTEST_FST',
test.t_dir + "/t_trace_two_cc.cpp"
])
test.execute()
if test.vlt_all:
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

39
test_regress/t/saif_tests/t_trace_two_portsaif_cc.py
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@ -1,39 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# Test tracing with two models instanced
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t_trace_two_a.v"
test.compile(make_main=False,
verilator_make_gmake=False,
top_filename='t_trace_two_b.v',
vm_prefix='Vt_trace_two_b',
verilator_flags2=['--trace-saif --trace-threads 1'])
test.run(
logfile=test.obj_dir + "/make_first_ALL.log",
cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"])
test.compile(make_main=False,
top_filename='t_trace_two_a.v',
verilator_flags2=[
'-exe', '--trace-saif --trace-threads 1', '-DTEST_FST',
test.t_dir + "/t_trace_two_cc.cpp"
],
v_flags2=['+define+TEST_DUMPPORTS'])
test.execute()
if test.vlt_all:
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

625
test_regress/t/t_trace_counter.out
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@ -1,625 +0,0 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$var wire 1 # clk $end
$var wire 8 $ state [7:0] $end
$scope module t $end
$var wire 1 # clk $end
$var wire 1 % rst $end
$var wire 8 $ state [7:0] $end
$var wire 32 & cyc [31:0] $end
$scope module c0 $end
$var wire 1 # clk $end
$var wire 1 % rst $end
$var wire 8 $ out [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0#
b00000000 $
0%
b00000000000000000000000000000000 &
#10
1#
1%
b00000000000000000000000000000001 &
#15
0#
#20
1#
b00000001 $
b00000000000000000000000000000010 &
#25
0#
#30
1#
b00000010 $
b00000000000000000000000000000011 &
#35
0#
#40
1#
b00000011 $
b00000000000000000000000000000100 &
#45
0#
#50
1#
b00000100 $
b00000000000000000000000000000101 &
#55
0#
#60
1#
b00000101 $
b00000000000000000000000000000110 &
#65
0#
#70
1#
b00000110 $
b00000000000000000000000000000111 &
#75
0#
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1#
b00000111 $
b00000000000000000000000000001000 &
#85
0#
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1#
b00001000 $
b00000000000000000000000000001001 &
#95
0#
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1#
b00001001 $
b00000000000000000000000000001010 &
#105
0#
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1#
b00001010 $
0%
b00000000000000000000000000001011 &
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0#
#120
1#
b00000000 $
1%
b00000000000000000000000000001100 &
#125
0#
#130
1#
b00000001 $
b00000000000000000000000000001101 &
#135
0#
#140
1#
b00000010 $
b00000000000000000000000000001110 &
#145
0#
#150
1#
b00000011 $
b00000000000000000000000000001111 &
#155
0#
#160
1#
b00000100 $
b00000000000000000000000000010000 &
#165
0#
#170
1#
b00000101 $
b00000000000000000000000000010001 &
#175
0#
#180
1#
b00000110 $
b00000000000000000000000000010010 &
#185
0#
#190
1#
b00000111 $
b00000000000000000000000000010011 &
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0#
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1#
b00001000 $
b00000000000000000000000000010100 &
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0#
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1#
b00001001 $
b00000000000000000000000000010101 &
#215
0#
#220
1#
b00001010 $
b00000000000000000000000000010110 &
#225
0#
#230
1#
b00001011 $
b00000000000000000000000000010111 &
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0#
#240
1#
b00001100 $
b00000000000000000000000000011000 &
#245
0#
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1#
b00001101 $
b00000000000000000000000000011001 &
#255
0#
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1#
b00001110 $
b00000000000000000000000000011010 &
#265
0#
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1#
b00001111 $
b00000000000000000000000000011011 &
#275
0#
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1#
b00010000 $
b00000000000000000000000000011100 &
#285
0#
#290
1#
b00010001 $
b00000000000000000000000000011101 &
#295
0#
#300
1#
b00010010 $
b00000000000000000000000000011110 &
#305
0#
#310
1#
b00010011 $
b00000000000000000000000000011111 &
#315
0#
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1#
b00010100 $
b00000000000000000000000000100000 &
#325
0#
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1#
b00010101 $
b00000000000000000000000000100001 &
#335
0#
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1#
b00010110 $
b00000000000000000000000000100010 &
#345
0#
#350
1#
b00010111 $
b00000000000000000000000000100011 &
#355
0#
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1#
b00011000 $
b00000000000000000000000000100100 &
#365
0#
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1#
b00011001 $
b00000000000000000000000000100101 &
#375
0#
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1#
b00011010 $
b00000000000000000000000000100110 &
#385
0#
#390
1#
b00011011 $
b00000000000000000000000000100111 &
#395
0#
#400
1#
b00011100 $
b00000000000000000000000000101000 &
#405
0#
#410
1#
b00011101 $
b00000000000000000000000000101001 &
#415
0#
#420
1#
b00011110 $
b00000000000000000000000000101010 &
#425
0#
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1#
b00011111 $
b00000000000000000000000000101011 &
#435
0#
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1#
b00100000 $
b00000000000000000000000000101100 &
#445
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1#
b00100001 $
b00000000000000000000000000101101 &
#455
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1#
b00100010 $
b00000000000000000000000000101110 &
#465
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1#
b00100011 $
b00000000000000000000000000101111 &
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1#
b00100100 $
b00000000000000000000000000110000 &
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1#
b00100101 $
b00000000000000000000000000110001 &
#495
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1#
b00100110 $
b00000000000000000000000000110010 &
#505
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#510
1#
b00100111 $
b00000000000000000000000000110011 &
#515
0#
#520
1#
b00101000 $
b00000000000000000000000000110100 &
#525
0#
#530
1#
b00101001 $
b00000000000000000000000000110101 &
#535
0#
#540
1#
b00101010 $
b00000000000000000000000000110110 &
#545
0#
#550
1#
b00101011 $
b00000000000000000000000000110111 &
#555
0#
#560
1#
b00101100 $
b00000000000000000000000000111000 &
#565
0#
#570
1#
b00101101 $
b00000000000000000000000000111001 &
#575
0#
#580
1#
b00101110 $
b00000000000000000000000000111010 &
#585
0#
#590
1#
b00101111 $
b00000000000000000000000000111011 &
#595
0#
#600
1#
b00110000 $
b00000000000000000000000000111100 &
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0#
#610
1#
b00110001 $
b00000000000000000000000000111101 &
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0#
#620
1#
b00110010 $
b00000000000000000000000000111110 &
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0#
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1#
b00110011 $
b00000000000000000000000000111111 &
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0#
#640
1#
b00110100 $
b00000000000000000000000001000000 &
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0#
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1#
b00110101 $
b00000000000000000000000001000001 &
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0#
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1#
b00110110 $
b00000000000000000000000001000010 &
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0#
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1#
b00110111 $
b00000000000000000000000001000011 &
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b00111000 $
b00000000000000000000000001000100 &
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0#
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1#
b00111001 $
b00000000000000000000000001000101 &
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1#
b00111010 $
b00000000000000000000000001000110 &
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0#
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1#
b00111011 $
b00000000000000000000000001000111 &
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0#
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1#
b00111100 $
b00000000000000000000000001001000 &
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0#
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1#
b00111101 $
b00000000000000000000000001001001 &
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0#
#740
1#
b00111110 $
b00000000000000000000000001001010 &
#745
0#
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1#
b00111111 $
b00000000000000000000000001001011 &
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1#
b01000000 $
b00000000000000000000000001001100 &
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0#
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1#
b01000001 $
b00000000000000000000000001001101 &
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1#
b01000010 $
b00000000000000000000000001001110 &
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0#
#790
1#
b01000011 $
b00000000000000000000000001001111 &
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0#
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1#
b01000100 $
b00000000000000000000000001010000 &
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0#
#810
1#
b01000101 $
b00000000000000000000000001010001 &
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0#
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1#
b01000110 $
b00000000000000000000000001010010 &
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0#
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1#
b01000111 $
b00000000000000000000000001010011 &
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0#
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1#
b01001000 $
b00000000000000000000000001010100 &
#845
0#
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1#
b01001001 $
b00000000000000000000000001010101 &
#855
0#
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1#
b01001010 $
b00000000000000000000000001010110 &
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0#
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1#
b01001011 $
b00000000000000000000000001010111 &
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0#
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1#
b01001100 $
b00000000000000000000000001011000 &
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1#
b01001101 $
b00000000000000000000000001011001 &
#895
0#
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1#
b01001110 $
b00000000000000000000000001011010 &
#905
0#
#910
1#
b01001111 $
b00000000000000000000000001011011 &
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0#
#920
1#
b01010000 $
b00000000000000000000000001011100 &
#925
0#
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1#
b01010001 $
b00000000000000000000000001011101 &
#935
0#
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1#
b01010010 $
b00000000000000000000000001011110 &
#945
0#
#950
1#
b01010011 $
b00000000000000000000000001011111 &
#955
0#
#960
1#
b01010100 $
b00000000000000000000000001100000 &
#965
0#
#970
1#
b01010101 $
b00000000000000000000000001100001 &
#975
0#
#980
1#
b01010110 $
b00000000000000000000000001100010 &
#985
0#
#990
1#
b01010111 $
b00000000000000000000000001100011 &
#995
0#
#1000
1#
b01011000 $
b00000000000000000000000001100100 &

27
test_regress/t/t_trace_counter.saif
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@ -1,27 +0,0 @@
(SAIFILE
(SAIFVERSION "2.0")
(DIRECTION "backward")
(DESIGN "foo")
(PROGRAM_NAME "Verilator")
(VERSION "5.032")
(DIVIDER .)
(TIMESCALE 1ps)
(DURATION 1000)
(INSTANCE foo (NET
(cyc[0] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
(cyc[1] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
(cyc[2] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25))
(cyc[3] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12))
(cyc[4] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
(cyc[5] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
(cyc[6] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
(rst (T0 20) (T1 980) (TZ 0) (TX 0) (TB 0) (TC 3))
(state[0] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 98))
(state[1] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 50))
(state[2] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 24))
(state[3] (T0 570) (T1 430) (TZ 0) (TX 0) (TB 0) (TC 13))
(state[4] (T0 600) (T1 400) (TZ 0) (TX 0) (TB 0) (TC 5))
(state[5] (T0 680) (T1 320) (TZ 0) (TX 0) (TB 0) (TC 2))
(state[6] (T0 760) (T1 240) (TZ 0) (TX 0) (TB 0) (TC 1))
(clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
)))

55
test_regress/t/t_trace_counter.v
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@ -1,55 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2025 by Antmicro. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t (
// Outputs
state,
// Inputs
clk);
input clk;
reg rst;
output [7:0] state;
counter c0 (
.clk (clk),
.rst (rst),
.out (state));
int cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
rst <= 1;
end
else if (cyc == 10) begin
rst <= 0;
end
else if (cyc == 11) begin
rst <= 1;
end
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module counter (
input clk,
input rst,
output reg[7:0] out);
always @ (posedge clk) begin
if (!rst)
out <= 0;
else
out <= out + 1;
end
endmodule