Tests: Convert t_loop into test_regress format

test_regress/t/t_EXAMPLE.v

@@ -87,7 +87,7 @@ module Test (/*AUTOARG*/
    // merge the output values into the result vector.
 
    input clk;
-   input [31:0]      in;
+   input [31:0] in;
    output reg [31:0] out;
 
    always @(posedge clk) begin

test_regress/t/t_for_loop.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_for_loop.v

@@ -3,15 +3,12 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_loop (/*AUTOARG*/
-   // Outputs
-   passed,
+module t (/*AUTOARG*/
    // Inputs
    clk
    );
 
    input clk;
-   output passed;  reg passed; initial passed = 0;
    reg [7:0] cyc; initial cyc=0;
 
    reg [31:0] loops;
@@ -53,8 +50,8 @@ module t_loop (/*AUTOARG*/
 	 end
 	 if (loops !== 100000) $stop;
 	 //
-	 $write("[%0t] t_loop: Passed\n",$time);
-	 passed <= 1'b1;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
       end
    end
 

test_v/t.v

@@ -80,11 +80,7 @@ module t (/*AUTOARG*/
       // Inputs
       .clk				(clk),
       .fastclk				(fastclk));
-   t_loop tloop
-     (.passed		(passedv[15]),
-      /*AUTOINST*/
-      // Inputs
-      .clk				(clk));
+   assign passedv[15] = 1'b1;
    assign passedv[16] = 1'b1;
    assign passedv[17] = 1'b1;
    assign passedv[18] = 1'b1;