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Fix false ASSIGNIN on interface input port connections (#7365) 

* add oneline fix

* Apply 'make format'

* merge test and update 2 space indents

---------

Co-authored-by: github action <action@example.com>
This commit is contained in:
Yilou Wang 2026-04-02 20:44:48 +02:00 committed by GitHub
parent 1e5c93cc51
commit 56ed47ee7c
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2 changed files with 35 additions and 8 deletions
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3
src/V3Width.cpp
View File

@ -2866,7 +2866,8 @@ class WidthVisitor final : public VNVisitor {
const bool netPort const bool netPort
= nodep->varp()->isNet() || nodep->varp()->varType() == VVarType::PORT; = nodep->varp()->isNet() || nodep->varp()->varType() == VVarType::PORT;
const bool contAssign = VN_IS(nodep->abovep(), AssignW); const bool contAssign = VN_IS(nodep->abovep(), AssignW);
if (!(hierRef && netPort && contAssign)) { const bool pinConn = VN_IS(nodep->abovep(), Pin);
if (!(hierRef && netPort && (contAssign || pinConn))) {
nodep->v3warn(ASSIGNIN, nodep->v3warn(ASSIGNIN,
"Assigning to input/const variable: " << nodep->prettyNameQ()); "Assigning to input/const variable: " << nodep->prettyNameQ());
} }

32
test_regress/t/t_interface_input_port_assign.v
View File

@ -9,9 +9,9 @@
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on // verilog_format: on
// Driving input ports from the instantiating scope via continuous assign // Driving interface net-type input ports from the instantiating scope is
// is legal when port kind defaults to net (IEEE 1800-2023 23.2.2.3). // legal via both continuous assignment and port connection when port kind
// All three forms below default to net for input ports. // defaults to net (IEEE 1800-2023 23.2.2.3, 23.3.3.3).
// Scenario 1: bare input (defaults to net) // Scenario 1: bare input (defaults to net)
interface bare_if ( interface bare_if (
@ -41,11 +41,32 @@ module consumer (
always @(posedge cif.clk) sampled <= cif.data; always @(posedge cif.clk) sampled <= cif.data;
endmodule endmodule
// Scenario 4: port connection driving interface input (AstPin path)
interface ifc_status (
input wire busy
);
endinterface
module dut (
output logic sleep_o
);
initial sleep_o = 1'b1;
endmodule
module dut_wrap (
ifc_status sif
);
dut u_dut (
.sleep_o(sif.busy)
);
endmodule
module t; module t;
logic clk = 0; logic clk = 0;
always #5 clk = ~clk; always #5 clk = ~clk;
integer cyc = 0; integer cyc = 0;
// Continuous assignment scenarios
bare_if bif (.clk()); bare_if bif (.clk());
assign bif.clk = clk; assign bif.clk = clk;
assign bif.data = 1'b1; assign bif.data = 1'b1;
@ -60,6 +81,10 @@ module t;
consumer cons (.cif(bif)); consumer cons (.cif(bif));
// Port connection scenario
ifc_status sif (.busy());
dut_wrap u_wrap (.sif(sif));
always @(posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc == 10) begin if (cyc == 10) begin
@ -69,6 +94,7 @@ module t;
`checkh(lif.data, 1'b1); `checkh(lif.data, 1'b1);
`checkh(wif.clk, clk); `checkh(wif.clk, clk);
`checkh(wif.data, 1'b1); `checkh(wif.data, 1'b1);
`checkh(sif.busy, 1'b1);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end