Merge f2e55c1cdf into 3b43b304a3
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commit
56a6cba6b7
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@ -3572,9 +3572,13 @@ class LinkDotResolveVisitor final : public VNVisitor {
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while (lookp) {
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while (lookp) {
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VSymEnt* const foundp = lookp->findIdFlat(name);
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VSymEnt* const foundp = lookp->findIdFlat(name);
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if (foundp && !VN_IS(foundp->nodep(), MemberDType)) {
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if (foundp && !VN_IS(foundp->nodep(), MemberDType)) {
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// A variable is not a type candidate (IEEE 1800-2023 6.18); skip it so an
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// Non-type entries are not type candidates
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// enclosing type is found, but keep it to preserve the "found: VAR" error.
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// (IEEE 1800-2023 6.18); skip them so an enclosing
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if (!VN_IS(foundp->nodep(), Var)) return foundp;
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// type is found, but keep one to preserve the "found: ..." error.
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if (VN_IS(foundp->nodep(), Typedef) || VN_IS(foundp->nodep(), ParamTypeDType)
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|| VN_IS(foundp->nodep(), Class)) {
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return foundp;
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}
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if (!shadowEntp) shadowEntp = foundp;
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if (!shadowEntp) shadowEntp = foundp;
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}
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}
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lookp = lookp->fallbackp();
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lookp = lookp->fallbackp();
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@ -0,0 +1,27 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class B;
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function void B();
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endfunction
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endclass
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class A;
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B b = B::new();
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function void B();
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b.B();
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$write("*-* All Finished *-*\n");
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$finish;
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endfunction
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endclass
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initial begin
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static A a = A::new();
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a.B();
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -34,12 +34,16 @@ class parent;
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rand my_blk my_blk;
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rand my_blk my_blk;
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endclass
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endclass
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class Cls;
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endclass
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module t;
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module t;
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my_t my_t; // also legal at module scope
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my_t my_t; // also legal at module scope
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initial begin
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initial begin
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static C c = new;
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static C c = new;
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static parent p = new;
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static parent p = new;
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static Cls Cls = new;
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c.my_t = 8'hAB;
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c.my_t = 8'hAB;
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p.my_blk = new;
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p.my_blk = new;
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p.my_blk.x = 5;
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p.my_blk.x = 5;
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