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Pawel Klopotek 2026-07-14 12:43:51 +00:00 committed by GitHub
commit 56a6cba6b7
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5 changed files with 56 additions and 3 deletions

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@ -3572,9 +3572,13 @@ class LinkDotResolveVisitor final : public VNVisitor {
while (lookp) { while (lookp) {
VSymEnt* const foundp = lookp->findIdFlat(name); VSymEnt* const foundp = lookp->findIdFlat(name);
if (foundp && !VN_IS(foundp->nodep(), MemberDType)) { if (foundp && !VN_IS(foundp->nodep(), MemberDType)) {
// A variable is not a type candidate (IEEE 1800-2023 6.18); skip it so an // Non-type entries are not type candidates
// enclosing type is found, but keep it to preserve the "found: VAR" error. // (IEEE 1800-2023 6.18); skip them so an enclosing
if (!VN_IS(foundp->nodep(), Var)) return foundp; // type is found, but keep one to preserve the "found: ..." error.
if (VN_IS(foundp->nodep(), Typedef) || VN_IS(foundp->nodep(), ParamTypeDType)
|| VN_IS(foundp->nodep(), Class)) {
return foundp;
}
if (!shadowEntp) shadowEntp = foundp; if (!shadowEntp) shadowEntp = foundp;
} }
lookp = lookp->fallbackp(); lookp = lookp->fallbackp();

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@ -0,0 +1,27 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t;
class B;
function void B();
endfunction
endclass
class A;
B b = B::new();
function void B();
b.B();
$write("*-* All Finished *-*\n");
$finish;
endfunction
endclass
initial begin
static A a = A::new();
a.B();
end
endmodule

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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

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@ -34,12 +34,16 @@ class parent;
rand my_blk my_blk; rand my_blk my_blk;
endclass endclass
class Cls;
endclass
module t; module t;
my_t my_t; // also legal at module scope my_t my_t; // also legal at module scope
initial begin initial begin
static C c = new; static C c = new;
static parent p = new; static parent p = new;
static Cls Cls = new;
c.my_t = 8'hAB; c.my_t = 8'hAB;
p.my_blk = new; p.my_blk = new;
p.my_blk.x = 5; p.my_blk.x = 5;