Internals: Fix removing nodes in V3Life (#5365)

src/V3Life.cpp

@@ -46,17 +46,13 @@ class LifeState final {
 public:
     VDouble0 m_statAssnDel;  // Statistic tracking
     VDouble0 m_statAssnCon;  // Statistic tracking
-    std::vector<AstNode*> m_unlinkps;
 
     // CONSTRUCTORS
     LifeState() = default;
     ~LifeState() {
         V3Stats::addStatSum("Optimizations, Lifetime assign deletions", m_statAssnDel);
         V3Stats::addStatSum("Optimizations, Lifetime constant prop", m_statAssnCon);
-        for (AstNode* ip : m_unlinkps) VL_DO_DANGLING(ip->unlinkFrBack()->deleteTree(), ip);
     }
-    // METHODS
-    void pushUnlinkDeletep(AstNode* nodep) { m_unlinkps.push_back(nodep); }
 };
 
 //######################################################################
@@ -124,6 +120,7 @@ class LifeBlock final {
     LifeBlock* const m_aboveLifep;  // Upper life, or nullptr
     LifeState* const m_statep;  // Current global state
     bool m_replacedVref = false;  // Replaced a variable reference since last clearing
+    VNDeleter m_deleter;  // Used to delay deletion of nodes
 
 public:
     LifeBlock(LifeBlock* aboveLifep, LifeState* statep)
@@ -145,7 +142,8 @@ public:
                 // above our current iteration point.
                 if (debug() > 4) oldassp->dumpTree("-      REMOVE/SAMEBLK: ");
                 entp->complexAssign();
-                VL_DO_DANGLING(m_statep->pushUnlinkDeletep(oldassp), oldassp);
+                oldassp->unlinkFrBack();
+                VL_DO_DANGLING(m_deleter.pushDeletep(oldassp), oldassp);
                 ++m_statep->m_statAssnDel;
             }
         }

test_regress/t/t_func_cond.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_func_cond.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  function automatic logic func_with_cond(logic x);
+    return x ? func_with_case(0) : 0;
+  endfunction
+
+  function automatic logic func_with_case(logic x);
+    logic result = 1'b0;
+    unique case (1'b0)
+      1'b0: result = x;
+      1'b1: result = x;
+    endcase
+    return result;
+  endfunction
+
+  initial begin
+    if (func_with_cond(0)) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule