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https://github.com/verilator/verilator.git
synced 2026-10-06 01:54:01 +02:00
Support 'real' numbers and related functions.
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+8
-2
@@ -545,6 +545,8 @@ public:
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ofp()->printf(",0x%08" VL_PRI64 "x", (vluint64_t)(nodep->num().dataWord(word)));
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}
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ofp()->printf(",0x%08" VL_PRI64 "x)", (vluint64_t)(nodep->num().dataWord(0)));
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} else if (nodep->isDouble()) {
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ofp()->printf("%g", nodep->num().toDouble());
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} else if (nodep->isQuad()) {
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vluint64_t num = nodep->toUQuad();
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if (num<10) ofp()->printf("VL_ULL(%" VL_PRI64 "d)", num);
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@@ -2013,7 +2015,9 @@ class EmitCTrace : EmitCStmts {
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return varp->isSc() && varp->isScBv();
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}
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void emitTraceInitOne(AstTraceDecl* nodep) {
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if (nodep->isWide()) {
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if (nodep->isDouble()) {
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puts("vcdp->declDouble");
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} else if (nodep->isWide()) {
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puts("vcdp->declArray");
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} else if (nodep->isQuad()) {
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puts("vcdp->declQuad ");
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@@ -2042,7 +2046,9 @@ class EmitCTrace : EmitCStmts {
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string full = ((m_funcp->funcType() == AstCFuncType::TRACE_FULL
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|| m_funcp->funcType() == AstCFuncType::TRACE_FULL_SUB)
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? "full":"chg");
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if (nodep->isWide() || emitTraceIsScBv(nodep)) {
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if (nodep->isDouble()) {
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puts("vcdp->"+full+"Double");
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} else if (nodep->isWide() || emitTraceIsScBv(nodep)) {
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puts("vcdp->"+full+"Array");
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} else if (nodep->isQuad()) {
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puts("vcdp->"+full+"Quad ");
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