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Remove implicit width 1 var creation. No functional change

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This commit is contained in:
Wilson Snyder
2009-07-16 14:06:53 -04:00
parent 4dde1ede0e
commit 556d90a1b4
3 changed files with 3 additions and 10 deletions
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src/V3Clock.cpp
+1 -1
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@@ -86,7 +86,7 @@ private:
if (varp->width()!=1) varp->v3error("Unsupported: Clock edge on non-single bit signal: "<<varp->prettyName());
string newvarname = ((string)"__Vclklast__"+vscp->scopep()->nameDotless()+"__"+varp->shortName());
AstVar* newvarp
= new AstVar (vscp->fileline(), AstVarType::MODULETEMP, newvarname); // No range; 1 bit.
= new AstVar (vscp->fileline(), AstVarType::MODULETEMP, newvarname, NULL, NULL); // No range; 1 bit.
newvarp->width(1,1);
m_modp->addStmtp(newvarp);
AstVarScope* newvscp = new AstVarScope(vscp->fileline(), m_scopep, newvarp);