Fix error when tracing public parameters, bug722.

Changes

@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix mis-optimization of bit-swap in wide signal, bug800. [Jie Xu]
 
+****  Fix error when tracing public parameters, bug722. [Jonathon Donaldson]
+
 
 * Verilator 3.862 2014-06-10
 

src/V3Param.cpp

@@ -210,7 +210,8 @@ private:
     virtual void visit(AstNodeModule* nodep, AstNUser*) {
 	if (nodep->dead()) {
 	    UINFO(4," MOD-dead.  "<<nodep<<endl);  // Marked by LinkDot
-	} else if (nodep->level() <= 2) {  // Haven't added top yet, so level 2 is the top
+	} else if (nodep->level() <= 2  // Haven't added top yet, so level 2 is the top
+		   || nodep->castPackage()) {	// Likewise haven't done wrapTopPackages yet
 	    // Add request to END of modules left to process
 	    m_todoModps.insert(make_pair(nodep->level(),nodep));
 	    visitModules();

test_regress/t/t_trace_param.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    v_flags2 => ["--trace"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_trace_param.v

@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Jonathon Donaldson.
+
+package my_funcs;
+   function automatic int simple_func (input int value);
+      begin
+	 simple_func = value;
+      end
+   endfunction
+endpackage
+
+package my_module_types;
+   import my_funcs::*;
+
+   localparam MY_PARAM = 3;
+   localparam MY_PARAM2 /*verilator public*/ = simple_func(12);
+endpackage
+
+module t
+  import my_module_types::*;
+   (
+    input 			i_clk,
+    input [MY_PARAM-1:0] 	i_d,
+    output logic [MY_PARAM-1:0] o_q
+    );
+
+   always_ff @(posedge i_clk)
+     o_q <= i_d;
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule