Commentary

docs/guide/contributors.rst

@@ -151,8 +151,8 @@ In 2018, Verilator 4.000 was released with multithreaded support.
 In 2019, Verilator joined the `CHIPS Alliance
 <https://chipsalliance.org>`_.
 
-In 2022, Verilator 5.000 was released with IEEE scheduling semantics
+In 2022, Verilator 5.000 was released with IEEE scheduling semantics,
-and other improvements.
+fork/join, delay handling, and other improvements.
 
 Currently, various language features and performance enhancements are added
 as the need arises.  Verilator is now about 3x faster than in 2002, and is

docs/guide/exe_verilator.rst

@@ -181,7 +181,7 @@ Summary:
    individual bits, Verilator will attempt to decompose the vector and
    connect the single-bit clock signals.
 
-   In versions prior to 5.002, the clocker attribute is useful in cases where
+   In versions prior to 5.000, the clocker attribute is useful in cases where
    Verilator does not properly distinguish clock signals from other data
    signals. Using clocker will cause the signal indicated to be considered a
    clock, and remove it from the combinatorial logic reevaluation checking
@@ -795,7 +795,7 @@ Summary:
 
    Deprecated and has no effect (ignored).
 
-   In versions prior to 5.002:
+   In versions prior to 5.000:
 
    Rarely needed.  Disables a bug fix for ordering of clock enables with
    delayed assignments.  This option should only be used when suggested by
@@ -1618,7 +1618,7 @@ The grammar of configuration commands is as follows:
 
    Deprecated and has no effect (ignored).
 
-   In versions prior to 5.002:
+   In versions prior to 5.000:
 
    Indicate the signal is used to gate a clock, and the user takes
    responsibility for insuring there are no races related to it.

docs/guide/extensions.rst

@@ -162,7 +162,7 @@ or "`ifdef`"'s may break other tools.
 
    Deprecated and has no effect (ignored).
 
-   In versions prior to 5.002:
+   In versions prior to 5.000:
 
    Used after a signal declaration to indicate the signal is used to gate a
    clock, and the user takes responsibility for insuring there are no races

docs/guide/warnings.rst

@@ -316,6 +316,20 @@ List Of Warnings
    potential for reset glitches.
 
 
+.. option:: CLKDATA
+
+   Historical, never issued since version 5.000.
+
+   Warned that clock signal was mixed used with/as data signal. The
+   checking for this warning was enabled only if user has explicitly marked
+   some signal as clocker using command line option or in-source meta
+   comment (see :vlopt:`--clk`).
+
+   The warning could be disabled without affecting the simulation
+   result. But it was recommended to check the warning as it may have
+   degrated the performance of the Verilated model.
+
+
 .. option:: CMPCONST
 
    .. TODO better example
@@ -577,6 +591,14 @@ List Of Warnings
    with a newline."
 
 
+.. option:: GENCLK
+
+   Historical, never issued since version 5.000.
+
+   Indicated that the specified signal was generated inside the model, and
+   was also being used as a clock.
+
+
 .. option:: HIERBLOCK
 
    Warns that the top module is marked as a hierarchy block by the
@@ -634,6 +656,16 @@ List Of Warnings
    simulate correctly.
 
 
+.. option:: IMPERFECTSCH
+
+   Historical, never issued since version 5.000.
+
+   Warned that the scheduling of the model is not absolutely perfect, and
+   some manual code edits may result in faster performance.  This warning
+   defaulted to off, was not part of -Wall, and had to be turned on
+   explicitly before the top module statement is processed.
+
+
 .. option:: IMPLICIT
 
    .. TODO better example
@@ -1362,6 +1394,16 @@ List Of Warnings
    undriven (...) and will be removed".
 
 
+.. option:: UNOPT
+
+   Historical, never issued since version 5.000.
+
+   Warned that due to some construct, optimization of the specified signal
+   or block was disabled.
+
+   Ignoring this warning only slowed simulations, it simulated correctly.
+
+
 .. option:: UNOPTFLAT
 
    .. TODO better example
@@ -1430,6 +1472,10 @@ List Of Warnings
    the :option:`/*verilator&32;isolate_assignments*/` metacomment described
    above.
 
+   Prior to version 5.000, the UNOPTFLAT warning may also have been due to
+   clock enables, identified from the reported path going through a clock
+   gating instance.  To fix these, the clock_enable meta comment was used.
+
    To assist in resolving UNOPTFLAT, the option :vlopt:`--report-unoptflat`
    can be used, which will provide suggestions for variables that can be
    split up, and a graph of all the nodes connected in the loop. See the
@@ -1700,32 +1746,3 @@ List Of Warnings
    Inactive region. Such processes do get resumed in the same time slot
    somewhere in the Active region. Issued only if Verilator is run with the
    :vlopt:`--timing` option.
-
-
-Historical Warnings
-===================
-
-The following list of warnings used to be issued by some earlier versions of
-Verilator. The current version never issues these warnings. For compatibility,
-these warning codes are still accepted by the message control mechanisms (see
-:ref:`Disabling Warnings`), but have no other effect.
-
-
-.. option:: CLKDATA
-
-   Historical, never issued by current version of Verilator.
-
-
-.. option:: GENCLK
-
-   Historical, never issued by current version of Verilator.
-
-
-.. option:: IMPERFECTSCH
-
-   Historical, never issued by current version of Verilator.
-
-
-.. option:: UNOPT
-
-   Historical, never issued by current version of Verilator.