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Support signal[vec]++.

This commit is contained in:
Wilson Snyder 2013-05-06 08:02:16 -04:00
parent ae6f5844da
commit 54eedcc739
3 changed files with 22 additions and 4 deletions
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@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
*** Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung] *** Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung]
**** Support "signal[vec]++".
**** Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell] **** Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell]
**** Fix module resolution with __, bug631. [Jason McMullan] **** Fix module resolution with __, bug631. [Jason McMullan]

8
src/verilog.y
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@ -2210,10 +2210,10 @@ foperator_assignment<nodep>: // IEEE: operator_assignment (for first part of exp
finc_or_dec_expression<nodep>: // ==IEEE: inc_or_dec_expression finc_or_dec_expression<nodep>: // ==IEEE: inc_or_dec_expression
//UNSUP: Generic scopes in incrementes //UNSUP: Generic scopes in incrementes
varRefBase yP_PLUSPLUS { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); } fexprLvalue yP_PLUSPLUS { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); }
| varRefBase yP_MINUSMINUS { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); } | fexprLvalue yP_MINUSMINUS { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); }
| yP_PLUSPLUS varRefBase { $$ = new AstAssign($1,$2,new AstAdd ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); } | yP_PLUSPLUS fexprLvalue { $$ = new AstAssign($1,$2,new AstAdd ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); }
| yP_MINUSMINUS varRefBase { $$ = new AstAssign($1,$2,new AstSub ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); } | yP_MINUSMINUS fexprLvalue { $$ = new AstAssign($1,$2,new AstSub ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); }
; ;
//************************************************ //************************************************

16
test_regress/t/t_math_const.v
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@ -12,6 +12,7 @@ module t (/*AUTOARG*/
reg [39:0] con1,con2, con3; reg [39:0] con1,con2, con3;
reg [31:0] w32; reg [31:0] w32;
reg [31:0] v32 [2];
// surefire lint_off UDDSCN // surefire lint_off UDDSCN
reg [200:0] conw3, conw4; reg [200:0] conw3, conw4;
@ -105,6 +106,21 @@ module t (/*AUTOARG*/
w32 = 12; w32 ^= 15; if (w32 != 3) $stop; w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop; w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop; w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
// Increments
v32[2] = 12; v32[2]++; if (v32[2] != 13) $stop;
v32[2] = 12; ++v32[2]; if (v32[2] != 13) $stop;
v32[2] = 12; v32[2]--; if (v32[2] != 11) $stop;
v32[2] = 12; --v32[2]; if (v32[2] != 11) $stop;
v32[2] = 12; v32[2] += 2; if (v32[2] != 14) $stop;
v32[2] = 12; v32[2] -= 2; if (v32[2] != 10) $stop;
v32[2] = 12; v32[2] *= 2; if (v32[2] != 24) $stop;
v32[2] = 12; v32[2] /= 2; if (v32[2] != 6) $stop;
v32[2] = 12; v32[2] &= 6; if (v32[2] != 4) $stop;
v32[2] = 12; v32[2] |= 15; if (v32[2] != 15) $stop;
v32[2] = 12; v32[2] ^= 15; if (v32[2] != 3) $stop;
v32[2] = 12; v32[2] >>= 1; if (v32[2] != 6) $stop;
v32[2] = 12; v32[2] <<= 1; if (v32[2] != 24) $stop;
end end
if (cyc==2) begin if (cyc==2) begin
win <= 32'h123123; win <= 32'h123123;