V3Const: Do not introduce redundant AstExtend

Fixes #3716

src/V3Const.cpp

@@ -2411,12 +2411,21 @@ private:
             VL_DO_DANGLING(lsb1p->deleteTree(), lsb1p);
             VL_DO_DANGLING(lsb2p->deleteTree(), lsb2p);
         } else {
-            // Width is important, we need the width of the fromp's
+            // Width is important, we need the width of the fromp's expression, not the
-            // expression, not the potentially smaller lsb1p's width
+            // potentially smaller lsb1p's width, but don't insert a redundant AstExtend.
-            newlsbp
+            // Note that due to some sloppiness in earlier passes, lsb1p might actually be wider,
-                = new AstAdd(lsb1p->fileline(), lsb2p, new AstExtend(lsb1p->fileline(), lsb1p));
+            // so extend to the wider type.
-            newlsbp->dtypeFrom(lsb2p);  // Unsigned
+            AstNode* const widep = lsb1p->width() > lsb2p->width() ? lsb1p : lsb2p;
-            VN_AS(newlsbp, Add)->rhsp()->dtypeFrom(lsb2p);
+            AstNode* const lhsp = widep->width() > lsb2p->width()
+                                      ? new AstExtend{lsb2p->fileline(), lsb2p}
+                                      : lsb2p;
+            AstNode* const rhsp = widep->width() > lsb1p->width()
+                                      ? new AstExtend{lsb1p->fileline(), lsb1p}
+                                      : lsb1p;
+            lhsp->dtypeFrom(widep);
+            rhsp->dtypeFrom(widep);
+            newlsbp = new AstAdd{lsb1p->fileline(), lhsp, rhsp};
+            newlsbp->dtypeFrom(widep);
         }
         AstSel* const newp = new AstSel(nodep->fileline(), fromp, newlsbp, widthp);
         nodep->replaceWith(newp);

test_regress/t/t_const_sel_sel_extend.pl

@@ -0,0 +1,16 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile();
+
+ok(1);
+1;

test_regress/t/t_const_sel_sel_extend.v

@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(
+  output wire res
+);
+
+   function automatic logic foo(logic bar);
+      foo = '0;
+   endfunction
+
+   logic       a, b;
+   logic [0:0][1:0] array;
+
+   assign b = 0;
+   assign a = foo(b);
+   assign res = array[a][a];
+
+endmodule