Fix nested union crash, bug643.

Changes

@@ -5,17 +5,19 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.847 devel
 
-***  Add ALWCOMBORDER warning.  [KC Buckenmaier]
-
-***  Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung]
-
-**** Support "signal[vec]++".
-
-**** Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell]
-
-**** Fix module resolution with __, bug631. [Jason McMullan]
-
-**** Fix packed array non-zero right index select crash, bug642. [Krzysztof Jankowski]
+***   Add ALWCOMBORDER warning.  [KC Buckenmaier]
+      
+***   Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung]
+      
+****  Support "signal[vec]++".
+      
+****  Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell]
+      
+****  Fix module resolution with __, bug631. [Jason McMullan]
+      
+****  Fix packed array non-zero right index select crash, bug642. [Krzysztof Jankowski]
+      
+****  Fix nested union crash, bug643. [Krzysztof Jankowski]
 
 
 * Verilator 3.846 2013-03-09

src/V3Width.cpp

@@ -1135,7 +1135,7 @@ private:
 	    } else {
 		AstSel* newp = new AstSel(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
 					  memberp->lsb(), memberp->width());
-		newp->dtypep(memberp);
+		newp->dtypep(memberp->skipRefp());  // Must skip over the member to find the union; as the member may disappear later
 		newp->didWidth(true);  // Don't replace dtype with basic type
 		UINFO(9,"   MEMBERSEL -> "<<newp<<endl);
 		nodep->replaceWith(newp);

test_regress/t/t_struct_nest.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    );
+
+ok(1);
+1;

test_regress/t/t_struct_nest.v

@@ -0,0 +1,45 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Wilson Snyder.
+
+typedef struct packed {
+    logic [1:0]  b1;
+    logic [1:0]  b2;
+    logic [1:0]  b3;
+    logic [1:0]  b4;
+} t__aa_bbbbbbb_ccccc_dddddd_eee;
+
+typedef struct packed {
+    logic [31:0] a;
+    union packed {
+       logic [7:0]                    fbyte;
+       t__aa_bbbbbbb_ccccc_dddddd_eee pairs;
+    } b1;
+    logic [23:0] b2;
+    logic [7:0] c1;
+    logic [23:0] c2;
+    logic [31:0] d;
+} t__aa_bbbbbbb_ccccc_dddddd;
+
+typedef struct packed {
+    logic [31:0] a;
+    logic [31:0] b;
+    logic [31:0] c;
+	logic [31:0] d;
+} t__aa_bbbbbbb_ccccc_eee;
+
+typedef union packed {
+    t__aa_bbbbbbb_ccccc_dddddd dddddd;
+    t__aa_bbbbbbb_ccccc_eee eee;
+} t__aa_bbbbbbb_ccccc;
+
+
+module t (
+    input t__aa_bbbbbbb_ccccc xxxxxxx_yyyyy_zzzz,
+    output logic [15:0] datao_pre
+);
+   always_comb datao_pre = { xxxxxxx_yyyyy_zzzz.dddddd.b1.fbyte, xxxxxxx_yyyyy_zzzz.dddddd.c1 };
+
+endmodule
+