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Fix bad-syntax crashes, bug1586, bug1587.

This commit is contained in:
Wilson Snyder 2019-11-04 21:51:20 -05:00
parent ca8da1f54f
commit 530ab17c8b
5 changed files with 75 additions and 30 deletions
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2
Changes
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@ -27,7 +27,7 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix multithreaded yield behavior when no work. [Patrick Stewart] **** Fix multithreaded yield behavior when no work. [Patrick Stewart]
**** Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563, **** Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563,
bug1573-1577, bug1582-1585, bug1589-1591. [Eric Rippey] bug1573-1577, bug1582-1591. [Eric Rippey]
**** Fix false CMPCONST/UNSIGNED warnings on "inside", bug1581. [Mitch Hayenga] **** Fix false CMPCONST/UNSIGNED warnings on "inside", bug1581. [Mitch Hayenga]

68
src/V3Slice.cpp
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@ -173,38 +173,48 @@ class SliceVisitor : public AstNVisitor {
UINFO(9, " Bi-Eq/Neq expansion "<<nodep<<endl); UINFO(9, " Bi-Eq/Neq expansion "<<nodep<<endl);
if (AstUnpackArrayDType* adtypep = VN_CAST(fromDtp, UnpackArrayDType)) { if (AstUnpackArrayDType* adtypep = VN_CAST(fromDtp, UnpackArrayDType)) {
AstNodeBiop* logp = NULL; AstNodeBiop* logp = NULL;
for (int index = 0; index < adtypep->rangep()->elementsConst(); ++index) { if (!VN_IS(nodep->lhsp()->dtypep()->skipRefp(), NodeArrayDType)) {
// EQ(a,b) -> LOGAND(EQ(ARRAYSEL(a,0), ARRAYSEL(b,0)), ...[1]) nodep->lhsp()->v3error("Slice operatator "<<nodep->lhsp()->prettyTypeName()
AstNodeBiop* clonep <<" on non-slicable (e.g. non-vector) left-hand-side operand");
= VN_CAST(nodep->cloneType }
(new AstArraySel(nodep->fileline(), else if (!VN_IS(nodep->rhsp()->dtypep()->skipRefp(), NodeArrayDType)) {
nodep->lhsp()->cloneTree(false), nodep->rhsp()->v3error("Slice operatator "<<nodep->rhsp()->prettyTypeName()
index), <<" on non-slicable (e.g. non-vector) right-hand-side operand");
new AstArraySel(nodep->fileline(), }
nodep->rhsp()->cloneTree(false), else {
index)), for (int index = 0; index < adtypep->rangep()->elementsConst(); ++index) {
NodeBiop); // EQ(a,b) -> LOGAND(EQ(ARRAYSEL(a,0), ARRAYSEL(b,0)), ...[1])
if (!logp) logp = clonep; AstNodeBiop* clonep
else { = VN_CAST(nodep->cloneType
switch (nodep->type()) { (new AstArraySel(nodep->fileline(),
case AstType::atEq: // FALLTHRU nodep->lhsp()->cloneTree(false),
case AstType::atEqCase: index),
logp = new AstLogAnd(nodep->fileline(), logp, clonep); new AstArraySel(nodep->fileline(),
break; nodep->rhsp()->cloneTree(false),
case AstType::atNeq: // FALLTHRU index)),
case AstType::atNeqCase: NodeBiop);
logp = new AstLogOr(nodep->fileline(), logp, clonep); if (!logp) logp = clonep;
break; else {
default: switch (nodep->type()) {
nodep->v3fatalSrc("Unknown node type processing array slice"); case AstType::atEq: // FALLTHRU
break; case AstType::atEqCase:
logp = new AstLogAnd(nodep->fileline(), logp, clonep);
break;
case AstType::atNeq: // FALLTHRU
case AstType::atNeqCase:
logp = new AstLogOr(nodep->fileline(), logp, clonep);
break;
default:
nodep->v3fatalSrc("Unknown node type processing array slice");
break;
}
} }
} }
UASSERT_OBJ(logp, nodep, "Unpacked array with empty indices range");
nodep->replaceWith(logp);
pushDeletep(nodep); VL_DANGLING(nodep);
nodep = logp;
} }
UASSERT_OBJ(logp, nodep, "Unpacked array with empty indices range");
nodep->replaceWith(logp);
pushDeletep(nodep); VL_DANGLING(nodep);
nodep = logp;
} }
iterateChildren(nodep); iterateChildren(nodep);
} }

5
test_regress/t/t_fuzz_eqne_bad.out Normal file
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@ -0,0 +1,5 @@
%Error: t/t_fuzz_eqne_bad.v:11: Slice operatator VARREF 't.b' on non-slicable (e.g. non-vector) right-hand-side operand
: ... In instance t.b
initial c = (a != &b);
^
%Error: Exiting due to

18
test_regress/t/t_fuzz_eqne_bad.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(linter => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

12
test_regress/t/t_fuzz_eqne_bad.v Normal file
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@ -0,0 +1,12 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
//bug1587
module t;
reg a[0];
reg b;
reg c;
initial c = (a != &b);
endmodule