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Remove pointless test 

t_optm_if_cond was a test for a then non-existent optimization to merge
conditionals. V3MergeCond implements this and has its own tests.
This commit is contained in:
Geza Lore 2023-10-21 20:24:20 +01:00
parent a09506a0ad
commit 52f2b9ef58
2 changed files with 0 additions and 79 deletions
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22
test_regress/t/t_optm_if_cond.pl
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@ -1,22 +0,0 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
verilator_flags2 => ['--stats', "-fno-merge-cond"],
);
if ($Self->{vlt_all}) {
file_grep($Self->{stats}, qr/Node count, IF +\d+ +\d+ +\d+ +\d+ +(\d+)/, 28);
}
ok(1);
1;

57
test_regress/t/t_optm_if_cond.v
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@ -1,57 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Outputs
q0, q1, q2, q3, q4,
// Inputs
clk, rst, en, i0, i1, i2, i3, i4
);
input clk;
input rst;
input en;
output int q0; input int i0;
output int q1; input int i1;
output int q2; input int i2;
output int q3; input int i3;
output int q4; input int i4;
always @ (posedge clk) begin
if (rst) begin
if (en) q0 <= i0;
end
else q0 <= 0;
if (rst) begin
if (en) q1 <= i1;
end
else q1 <= 0;
if (rst) begin
if (en) q2 <= i2;
end
else q2 <= 0;
if (rst) begin
if (en) q3 <= i3;
end
else q3 <= 0;
end
always_comb begin
q4 = i4;
if (q4 == 0) begin
// Conflicts with condition
q4 = 1;
end
if (q4 == 0) begin
// Conflicts with condition
q4 = 2;
end
end
endmodule