Merge from master

Changes

@@ -21,6 +21,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Add OBJCACHE envvar support to examples and generated Makefiles.
 
+****  Fix define argument stringification (`"), broke since 3.914. [Joe DErrico]
+
 
 * Verilator 3.924 2018-06-12
 

src/V3PreLex.l

@@ -208,7 +208,7 @@ drop		[\032]
 <ARGMODE>{crnl}		{ linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
 <ARGMODE>{quote}	{ yy_push_state(STRMODE); yymore(); }
 <ARGMODE>"`\\`\""	{ appendDefValue(yytext,yyleng); }  /* Literal text */
-<ARGMODE>{tickquote}	{ return(VP_STRIFY); }
+<ARGMODE>{tickquote}	{ yy_push_state(STRIFY); return(VP_STRIFY); }
 <ARGMODE>[{\[]		{ LEXP->m_parenLevel++; appendDefValue(yytext,yyleng); }
 <ARGMODE>[}\]]		{ LEXP->m_parenLevel--; appendDefValue(yytext,yyleng); }
 <ARGMODE>[(]		{ LEXP->m_parenLevel++;

src/V3PreProc.cpp

@@ -1127,6 +1127,10 @@ int V3PreProcImp::getStateToken() {
 		string rtn; rtn.assign(yyourtext(),yyourleng());
 		refp->nextarg(refp->nextarg()+rtn);
 		goto next_tok;
+            } else if (tok==VP_STRIFY) {
+                // We must expand stringinfication, when done will return to this state
+                statePush(ps_STRIFY);
+                goto next_tok;
 	    } else {
 		error((string)"Expecting ) or , to end argument list for define reference. Found: "+tokenName(tok));
 		statePop();

test_regress/t/t_gate_tree.pl

@@ -0,0 +1,123 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+use IO::File;
+#use Data::Dumper;
+use strict;
+use vars qw($Self);
+
+scenarios(simulator => 1);
+
+my $width = 64*($ENV{VERILATOR_TEST_WIDTH}||4);
+my $vars = 64;
+
+$Self->{cycles} = ($Self->{benchmark} ? 1_000_000 : 100);
+$Self->{sim_time} = $Self->{cycles} * 10 + 1000;
+
+sub gen {
+    my $filename = shift;
+
+    my $fh = IO::File->new(">$filename");
+    $fh->print("// Generated by t_gate_tree.pl\n");
+    $fh->print("module t (clk);\n");
+    $fh->print("  input clk;\n");
+    $fh->print("\n");
+    $fh->print("  integer cyc=0;\n");
+    $fh->print("  reg reset;\n");
+    $fh->print("\n");
+
+    my %tree;
+    my $fanin = 8;
+    my $stages = int(log($vars)/log($fanin)+0.99999)+1;
+    my $result = 0;
+    for (my $n=0; $n<$vars; $n++) {
+        $result += ($n||1);
+        $tree{0}{$n}{$n} = 1;
+        my $nl = $n;
+        for (my $stage=1; $stage<$stages; $stage++) {
+            my $lastn = $nl;
+            $nl = int($nl/$fanin);
+            $tree{$stage}{$nl}{$lastn} = 1;
+        }
+    }
+    #print Dumper(\%tree);
+
+    $fh->print("\n");
+    my $workingset = 0;
+    foreach my $stage (sort {$a<=>$b} keys %tree) {
+        foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) {
+            $fh->print(    "   reg [".($width-1).":0] v${stage}_${n};\n");
+            $workingset += int($width/8 + 7);
+        }
+    }
+
+    $fh->print("\n");
+    $fh->print("   always @ (posedge clk) begin\n");
+    $fh->print("      cyc <= cyc + 1;\n");
+    $fh->print("`ifdef TEST_VERBOSE\n");
+    $fh->print("         \$write(\"[%0t] rst=%0x  v0_0=%0x  v1_0=%0x  result=%0x\\n\""
+               .", \$time, reset, v0_0, v1_0, v".($stages-1)."_0);\n");
+    $fh->print("`endif\n");
+    $fh->print("      if (cyc==0) begin\n");
+    $fh->print("         reset <= 1;\n");
+    $fh->print("      end\n");
+    $fh->print("      else if (cyc==10) begin\n");
+    $fh->print("         reset <= 0;\n");
+    $fh->print("      end\n");
+    $fh->print("`ifndef SIM_CYCLES\n");
+    $fh->print(" `define SIM_CYCLES 99\n");
+    $fh->print("`endif\n");
+    $fh->print("      else if (cyc==`SIM_CYCLES) begin\n");
+    $fh->print("         if (v".($stages-1)."_0 != ${width}'d${result}) \$stop;\n");
+    $fh->print("         \$write(\"VARS=${vars} WIDTH=${width}"
+               ." WORKINGSET=".(int($workingset/1024))."KB\\n\");\n");
+    $fh->print('         $write("*-* All Finished *-*\n");',"\n");
+    $fh->print('         $finish;',"\n");
+    $fh->print("      end\n");
+    $fh->print("   end\n");
+
+    $fh->print("\n");
+    for (my $n=0; $n<$vars; $n++) {
+        $fh->print("   always @ (posedge clk)"
+                   ." v0_${n} <= reset ? ${width}'d".(${n}||1)." : v0_"
+                   .((int($n/$fanin)*$fanin) + (($n+1) % $fanin)).";\n");
+    }
+
+    foreach my $stage (sort {$a<=>$b} keys %tree) {
+        next if $stage == 0;
+        $fh->print("\n");
+        foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) {
+            $fh->print("   always @ (posedge clk)"
+                       ." v${stage}_${n} <=");
+            my $op = "";
+            foreach my $ni (sort {$a<=>$b} keys %{$tree{$stage}{$n}}) {
+                $fh->print($op." v".(${stage}-1)."_${ni}");
+                $op = " +";
+            }
+            $fh->print(";\n");
+        }
+    }
+
+    $fh->print("endmodule\n");
+}
+
+top_filename("$Self->{obj_dir}/t_gate_tree.v");
+
+gen($Self->{top_filename});
+
+compile(
+    v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",],
+    verilator_flags2=>["--stats --x-assign fast --x-initial fast"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_mem_multi_io2.cpp

@@ -19,7 +19,12 @@ void check(const char* bus, int got, int exp) {
     }
 }
 
-int main() {
+#ifdef SYSTEMC_VERSION
+int sc_main(int, char**)
+#else
+int main()
+#endif
+{
     Verilated::debug(0);
     tb = new VM_PREFIX ("tb");
 

test_regress/t/t_mem_multi_io3.cpp

@@ -12,7 +12,12 @@ double sc_time_stamp() {
     return 0;
 }
 
-int main() {
+#ifdef SYSTEMC_VERSION
+int sc_main(int, char**)
+#else
+int main()
+#endif
+{
     Verilated::debug(0);
     tb = new VM_PREFIX ("tb");
 

test_regress/t/t_preproc.out

@@ -899,6 +899,38 @@ XYS_FAMILY = XYS_foo
 `line 614 "t/t_preproc.v" 0
  
  
+
+`line 617 "t/t_preproc.v" 0
+ 
+`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
+
+`line 620 "t/t_preproc.v" 0
+ 
+ 
+
+ 
+
+
+
+
+`line 628 "t/t_preproc.v" 0
+module pcc2_cfg;
+  generate
+   
+`line 630 "t/t_preproc.v" 0
+  covergroup a @(posedge b); 
+`line 630 "t/t_preproc.v" 0
+    c: coverpoint d iff ((c) === 1'b1); endgroup 
+`line 630 "t/t_preproc.v" 0
+      a u_a; 
+`line 630 "t/t_preproc.v" 0
+   initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
+  endgenerate
+endmodule
+
+`line 634 "t/t_preproc.v" 0
+ 
+ 
    
 predef 0 0
 predef 1 1
@@ -917,4 +949,4 @@ predef 1 1
 predef 2 2
  
 
-`line 634 "t/t_preproc.v" 2
+`line 654 "t/t_preproc.v" 2

test_regress/t/t_preproc.v

@@ -611,6 +611,26 @@ NYS_FAMILY = `NYS_FAMILY
 `define INSTANCE(NAME) (.mySig (myInterface.``NAME),
 `INSTANCE(pa5)
 
+//======================================================================
+// Stringify bug
+
+`define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`"));
+`hack(paramgrp)
+
+`define dbg_hdl(LVL, MSG)      $display ("DEBUG : %s [%m]", $sformatf MSG)
+`define svfcov_new(GRP) \
+   initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0)
+`define simple_svfcov_clk(LBL, CLK, RST, ARG) \
+  covergroup LBL @(posedge CLK); \
+    c: coverpoint ARG iff ((RST) === 1'b1); endgroup \
+      LBL u_``LBL; `svfcov_new(u_``LBL)
+
+module pcc2_cfg;
+  generate
+   `simple_svfcov_clk(a, b, c, d);
+  endgenerate
+endmodule
+
 //======================================================================
 // IEEE mandated predefines
 `undefineall  // undefineall should have no effect on these