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Internals: Add const. No functional change.

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This commit is contained in:
Wilson Snyder
2021-06-20 18:33:13 -04:00
parent ec4eb18846
commit 512fe0a2d1
87 changed files with 690 additions and 669 deletions
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src/V3Number.cpp
+26 -26
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@@ -100,7 +100,7 @@ V3Number::V3Number(VerilogStringLiteral, AstNode* nodep, const string& str) {
init(nodep, str.length() * 8);
m_fromString = true;
for (unsigned pos = 0; pos < str.length(); ++pos) {
int topos = str.length() - 1 - pos;
const int topos = str.length() - 1 - pos;
for (int bit = 0; bit < 8; ++bit) {
if (str[pos] & (1UL << bit)) {
m_value[topos / 4] |= (1UL << (bit + (topos % 4) * 8));
@@ -515,10 +515,10 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const {
if (isSigned()) out << "s";
}
bool binary = (isFourState()
const bool binary = (isFourState()
#ifdef V3NUMBER_ASCII_BINARY
// cppcheck-suppress konwnConditionTrueFalse
|| true
// cppcheck-suppress konwnConditionTrueFalse
|| true
#endif
);
// out<<"-"<<hex<<m_value[0]<<"-";
@@ -586,7 +586,7 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const {
fmtsize += pos[0];
}
string str;
char code = tolower(pos[0]);
const char code = tolower(pos[0]);
switch (code) {
case 'b': {
int bit = width() - 1;
@@ -655,14 +655,14 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const {
if (fmtsize != "0") str += ' ';
}
}
size_t fmtsizen = static_cast<size_t>(atoi(fmtsize.c_str()));
const size_t fmtsizen = static_cast<size_t>(atoi(fmtsize.c_str()));
str = displayPad(fmtsizen, ' ', left, str);
return str;
}
case '~': // Signed decimal
case 't': // Time
case 'd': { // Unsigned decimal
bool issigned = (code == '~');
const bool issigned = (code == '~');
if (fmtsize == "") {
const double mantissabits = this->width() - (issigned ? 1 : 0);
// To get the number of digits required, we want to compute
@@ -686,9 +686,9 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const {
str = cvtToStr(toUQuad());
}
}
bool zeropad = fmtsize.length() > 0 && fmtsize[0] == '0';
const bool zeropad = fmtsize.length() > 0 && fmtsize[0] == '0';
// fmtsize might have changed since we parsed the %fmtsize
size_t fmtsizen = static_cast<size_t>(atoi(fmtsize.c_str()));
const size_t fmtsizen = static_cast<size_t>(atoi(fmtsize.c_str()));
str = displayPad(fmtsizen, (zeropad ? '0' : ' '), left, str);
return str;
}
@@ -741,7 +741,7 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const {
return str;
}
case '@': { // Packed string
size_t fmtsizen = static_cast<size_t>(atoi(fmtsize.c_str()));
const size_t fmtsizen = static_cast<size_t>(atoi(fmtsize.c_str()));
str = displayPad(fmtsizen, ' ', left, toString());
return str;
}
@@ -762,7 +762,7 @@ string V3Number::toDecimalS() const {
}
string V3Number::toDecimalU() const {
int maxdecwidth = (width() + 3) * 4 / 3;
const int maxdecwidth = (width() + 3) * 4 / 3;
// Or (maxdecwidth+7)/8], but can't have more than 4 BCD bits per word
V3Number bcd(this, maxdecwidth + 4);
@@ -1161,7 +1161,7 @@ V3Number& V3Number::opCLog2(const V3Number& lhs) {
NUM_ASSERT_LOGIC_ARGS1(lhs);
if (lhs.isFourState()) return setAllBitsX();
// IE if 4, this algorithm didn't pre-subtract 1, so we need to post-correct now
int adjust = (lhs.countOnes() == 1) ? 0 : 1;
const int adjust = (lhs.countOnes() == 1) ? 0 : 1;
for (int bit = lhs.width() - 1; bit >= 0; bit--) {
if (lhs.bitIs1(bit)) {
setLong(bit + adjust);
@@ -1331,9 +1331,9 @@ V3Number& V3Number::opStreamL(const V3Number& lhs, const V3Number& rhs) {
v3warn(WIDTHCONCAT, "Unsized numbers/parameters not allowed in streams.");
}
// Slice size should never exceed the lhs width
int ssize = std::min(rhs.toUInt(), static_cast<unsigned>(lhs.width()));
const int ssize = std::min(rhs.toUInt(), static_cast<unsigned>(lhs.width()));
for (int istart = 0; istart < lhs.width(); istart += ssize) {
int ostart = std::max(0, lhs.width() - ssize - istart);
const int ostart = std::max(0, lhs.width() - ssize - istart);
for (int bit = 0; bit < ssize && bit < lhs.width() - istart; bit++) {
setBit(ostart + bit, lhs.bitIs(istart + bit));
}
@@ -1472,8 +1472,8 @@ V3Number& V3Number::opCompareNN(const V3Number& lhs, const V3Number& rhs, bool i
// SystemVerilog Language Standard does not allow a string variable to contain '\0'.
// So C functions such as strcmp() can correctly compare strings.
int result;
string lstring = lhs.toString();
string rstring = rhs.toString();
const string lstring = lhs.toString();
const string rstring = rhs.toString();
if (ignoreCase) {
result = VL_STRCASECMP(lstring.c_str(), rstring.c_str());
} else {
@@ -1609,7 +1609,7 @@ V3Number& V3Number::opGtS(const V3Number& lhs, const V3Number& rhs) {
NUM_ASSERT_LOGIC_ARGS2(lhs, rhs);
char outc = 0;
{
int mbit = std::max(lhs.width() - 1, rhs.width() - 1);
const int mbit = std::max(lhs.width() - 1, rhs.width() - 1);
if (lhs.bitIsXZ(mbit)) {
outc = 'x';
} else if (rhs.bitIsXZ(mbit)) {
@@ -1735,7 +1735,7 @@ V3Number& V3Number::opAdd(const V3Number& lhs, const V3Number& rhs) {
// Addem
int carry = 0;
for (int bit = 0; bit < this->width(); bit++) {
int sum = ((lhs.bitIs1(bit) ? 1 : 0) + (rhs.bitIs1(bit) ? 1 : 0) + carry);
const int sum = ((lhs.bitIs1(bit) ? 1 : 0) + (rhs.bitIs1(bit) ? 1 : 0) + carry);
if (sum & 1) setBit(bit, 1);
carry = (sum >= 2);
}
@@ -1871,7 +1871,7 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
NUM_ASSERT_LOGIC_ARGS2(lhs, rhs);
setZero();
// Find MSB and check for zero.
int words = lhs.words();
const int words = lhs.words();
int umsbp1 = lhs.mostSetBitP1(); // dividend
int vmsbp1 = rhs.mostSetBitP1(); // divisor
if (VL_UNLIKELY(vmsbp1 == 0) // rwp==0 so division by zero. Return 0.
@@ -1880,8 +1880,8 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
return *this;
}
int uw = (umsbp1 + 31) / 32; // aka "m" in the algorithm
int vw = (vmsbp1 + 31) / 32; // aka "n" in the algorithm
const int uw = (umsbp1 + 31) / 32; // aka "m" in the algorithm
const int vw = (vmsbp1 + 31) / 32; // aka "n" in the algorithm
if (vw == 1) { // Single divisor word breaks rest of algorithm
vluint64_t k = 0;
@@ -2084,7 +2084,7 @@ V3Number& V3Number::opExtendS(const V3Number& lhs, uint32_t lbits) {
NUM_ASSERT_LOGIC_ARGS1(lhs);
setZero();
for (int bit = 0; bit < width(); bit++) {
char extendWith = lhs.bitIsExtend(bit, lbits);
const char extendWith = lhs.bitIsExtend(bit, lbits);
setBit(bit, extendWith);
}
return *this;
@@ -2170,7 +2170,7 @@ V3Number& V3Number::opIToRD(const V3Number& lhs, bool isSigned) {
V3Number noxz(lhs);
noxz.opAssignNonXZ(lhs);
double d = 0;
bool negate = isSigned && noxz.isNegative();
const bool negate = isSigned && noxz.isNegative();
if (negate) {
V3Number noxz_signed = noxz;
noxz.opNegate(noxz_signed);
@@ -2201,15 +2201,15 @@ V3Number& V3Number::opRToIRoundS(const V3Number& lhs) {
u.d = v;
if (u.d == 0.0) {}
int exp = static_cast<int>((u.q >> 52ULL) & VL_MASK_Q(11)) - 1023;
int lsb = exp - 52;
const int exp = static_cast<int>((u.q >> 52ULL) & VL_MASK_Q(11)) - 1023;
const int lsb = exp - 52;
vluint64_t mantissa = (u.q & VL_MASK_Q(52)) | (1ULL << 52);
if (v != 0) {
// IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa
// This does not need to support subnormals as they are sub-integral
for (int bit = 0; bit <= 52; ++bit) {
if (mantissa & (1ULL << bit)) {
int outbit = bit + lsb;
const int outbit = bit + lsb;
if (outbit >= 0) setBit(outbit, 1);
}
}