Fix duplicate name error with interface initial blocks (#6804) (#6805).

This commit is contained in:
Thomas Dybdahl Ahle 2025-12-16 20:57:58 -05:00 committed by Wilson Snyder
parent 41c4f948fe
commit 5115be6e6b
5 changed files with 57 additions and 0 deletions

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@ -109,6 +109,7 @@ Verilator 5.043 devel
* Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.] * Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.]
* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore] * Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande] * Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
Verilator 5.042 2025-11-02 Verilator 5.042 2025-11-02

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@ -233,6 +233,7 @@ Steven Hugg
Szymon Gizler Szymon Gizler
Sören Tempel Sören Tempel
Teng Huang Teng Huang
Thomas Dybdahl Ahle
Tim Hutt Tim Hutt
Tim Snyder Tim Snyder
Tobias Jensen Tobias Jensen

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@ -101,6 +101,9 @@ private:
} }
} }
void memberInsert(MemberMap& mmapr, AstNode* childp, bool warn = true) { void memberInsert(MemberMap& mmapr, AstNode* childp, bool warn = true) {
// Skip nodes without names (e.g., initial blocks, anonymous statements)
// These can't be looked up by name anyway
if (childp->name().empty()) return;
const auto mitPair = mmapr.emplace(childp->name(), childp); const auto mitPair = mmapr.emplace(childp->name(), childp);
if (VL_UNCOVERABLE(!mitPair.second && warn)) { if (VL_UNCOVERABLE(!mitPair.second && warn)) {
// Probably an internal error, but we'll make it user friendly if happens // Probably an internal error, but we'll make it user friendly if happens

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@ -0,0 +1,17 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.top_filename = "t/t_interface_initial.v"
test.lint()
test.passes()

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@ -0,0 +1,35 @@
// DESCRIPTION: Verilator: Test interface with multiple initial blocks
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Test that interfaces with multiple initial blocks don't cause
// "Duplicate declaration of member name: ''" errors when a method
// is called on the interface (which triggers VMemberMap::findMember).
// Initial blocks have empty names, so the member map should skip them.
interface my_iface;
int value;
// Multiple initial blocks (anonymous - have empty names)
initial value = 0;
initial $display("Init 1");
initial $display("Init 2");
// A method that can be called to trigger member map lookup
function int get_value();
return value;
endfunction
endinterface
module t;
my_iface iface ();
initial begin
// This method call triggers VMemberMap::findMember on the interface
if (iface.get_value() !== 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule