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@ -109,6 +109,7 @@ Verilator 5.043 devel
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* Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.]
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* Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.]
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* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
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* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
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* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
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* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
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* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
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Verilator 5.042 2025-11-02
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Verilator 5.042 2025-11-02
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@ -233,6 +233,7 @@ Steven Hugg
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Szymon Gizler
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Szymon Gizler
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Sören Tempel
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Sören Tempel
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Teng Huang
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Teng Huang
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Thomas Dybdahl Ahle
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Tim Hutt
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Tim Hutt
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Tim Snyder
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Tim Snyder
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Tobias Jensen
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Tobias Jensen
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@ -101,6 +101,9 @@ private:
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}
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}
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}
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}
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void memberInsert(MemberMap& mmapr, AstNode* childp, bool warn = true) {
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void memberInsert(MemberMap& mmapr, AstNode* childp, bool warn = true) {
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// Skip nodes without names (e.g., initial blocks, anonymous statements)
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// These can't be looked up by name anyway
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if (childp->name().empty()) return;
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const auto mitPair = mmapr.emplace(childp->name(), childp);
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const auto mitPair = mmapr.emplace(childp->name(), childp);
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if (VL_UNCOVERABLE(!mitPair.second && warn)) {
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if (VL_UNCOVERABLE(!mitPair.second && warn)) {
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// Probably an internal error, but we'll make it user friendly if happens
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// Probably an internal error, but we'll make it user friendly if happens
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@ -0,0 +1,17 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.top_filename = "t/t_interface_initial.v"
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test.lint()
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test.passes()
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@ -0,0 +1,35 @@
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// DESCRIPTION: Verilator: Test interface with multiple initial blocks
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test that interfaces with multiple initial blocks don't cause
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// "Duplicate declaration of member name: ''" errors when a method
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// is called on the interface (which triggers VMemberMap::findMember).
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// Initial blocks have empty names, so the member map should skip them.
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interface my_iface;
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int value;
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// Multiple initial blocks (anonymous - have empty names)
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initial value = 0;
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initial $display("Init 1");
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initial $display("Init 2");
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// A method that can be called to trigger member map lookup
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function int get_value();
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return value;
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endfunction
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endinterface
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module t;
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my_iface iface ();
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initial begin
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// This method call triggers VMemberMap::findMember on the interface
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if (iface.get_value() !== 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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