[#73220] add t_trace_complex_params_saif tests
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Mateusz Gancarz
parent
0ee40fe1a9
commit
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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "t")
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(DIVIDER / )
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(TIMESCALE 1ps)
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(DURATION 60)
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(INSTANCE top
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(NET
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)
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(INSTANCE $unit
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(NET
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)
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(INSTANCE t
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(NET
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(v_enumed2\[3\] (T0 40) (T1 20) (TX 0) (TC 1))
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(v_enumb\[0\] (T0 30) (T1 30) (TX 0) (TC 6))
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(v_enumb2_str\[4\] (T0 40) (T1 20) (TX 0) (TC 3))
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(v_enumb2_str\[5\] (T0 20) (T1 40) (TX 0) (TC 2))
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)
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(INSTANCE a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed
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(NET
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(PARAM\[2\] (T0 0) (T1 60) (TX 0) (TC 1))
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)
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)
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(INSTANCE p2
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(NET
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(PARAM\[1\] (T0 0) (T1 60) (TX 0) (TC 1))
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)
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)
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(INSTANCE p3
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(NET
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(PARAM\[0\] (T0 0) (T1 60) (TX 0) (TC 1))
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(PARAM\[1\] (T0 0) (T1 60) (TX 0) (TC 1))
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)
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)
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(INSTANCE unnamedblk1
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(NET
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(b\[0\] (T0 10) (T1 50) (TX 0) (TC 1))
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(b\[2\] (T0 10) (T1 50) (TX 0) (TC 1))
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)
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(INSTANCE unnamedblk2
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(NET
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(a\[0\] (T0 10) (T1 50) (TX 0) (TC 1))
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(a\[2\] (T0 10) (T1 50) (TX 0) (TC 1))
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)
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)
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)
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)
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)
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)
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@ -0,0 +1,22 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_trace_complex.v"
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test.golden_filename = "t/t_trace_complex_params_saif.out"
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test.compile(verilator_flags2=['--cc --trace-saif --no-trace-structs --trace-params'])
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test.execute()
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test.saif_identical(test.trace_filename, test.golden_filename)
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test.passes()
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